JAJSIB2 December 2019 ADC3421-Q1
PRODUCTION DATA.
Device is equipped with a mode to verify presence of a valid input clock, as well as status of on-chip ADC reference. When a valid clock input clock is absent at input clock pins (CLKP,CLKM) of ADC, device sets register bit CLK STATUS to ‘1’. Similarly, if internal reference block is malfunctioning for a channel, device sets register bits REF STATUS CHx to ‘1’. To read the status of internal reference from these pins: