JAJSIB2 December 2019 ADC3421-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLK DIV | 0 | 0 | 0 | 0 | 0 | 0 | |
R/W-0h | W-0h | W-0h | W-0h | W-0h | W-0h | W-0h |
LEGEND: R/W = Read/Write; W = Write only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-6 | CLK DIV | R/W | 0h | These bits select the internal clock divider for the input sampling clock.
00 = Divide-by-1 01 = Divide-by-1 10 = Divide-by-2 11 = Divide-by-4 |
5-0 | 0 | W | 0h | Must write 0. |