SBAS669A May   2014  – January 2015 ADC34J22 , ADC34J23 , ADC34J24 , ADC34J25

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Summary of Special Mode Registers
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics: ADC34J24, ADC34J25
    7. 7.7  Electrical Characteristics: ADC34J22, ADC34J23
    8. 7.8  Electrical Characteristics: General
    9. 7.9  AC Performance: ADC34J25
    10. 7.10 AC Performance: ADC34J24
    11. 7.11 AC Performance: ADC34J23
    12. 7.12 AC Performance: ADC34J22
    13. 7.13 Digital Characteristics
    14. 7.14 Timing Characteristics
    15. 7.15 Typical Characteristics: ADC34J25
    16. 7.16 Typical Characteristics: ADC34J24
    17. 7.17 Typical Characteristics: ADC34J23
    18. 7.18 Typical Characteristics: ADC34J22
    19. 7.19 Typical Characteristics: Common Plots
    20. 7.20 Typical Characteristics: Contour Plots
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
        2. 9.3.2.2 Input Clock Divider
      3. 9.3.3 Power-Down Control
      4. 9.3.4 Internal Dither Algorithm
      5. 9.3.5 JESD204B Interface
        1. 9.3.5.1 JESD204B Initial Lane Alignment (ILA)
        2. 9.3.5.2 JESD204B Test Patterns
        3. 9.3.5.3 JESD204B Frame Assembly
        4. 9.3.5.4 Digital Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Gain
      2. 9.4.2 Overrange Indication
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
      3. 9.5.3 Start-Up Sequence
    6. 9.6 Register Map
      1. 9.6.1 Serial Register Description
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8 Parameter Measurement Information

8.1 Timing Diagrams

tim_adc_latency_bas663.gif
1. Overall latency = ADC latency + tD.
2. x = A for channel A and B for channel B.
Figure 143. ADC Latency
tim_sync_cgs_bas669.gif
1. x = A for channel A, B for channel B, C for channel C, and D for channel D.
Figure 144. SYNC~ Latency in CGS Phase (Two-Lane Mode)
tim_sync_ilas_bas669.gif
1. x = A for channel A, B for channel B, C for channel C, and D for channel D.
Figure 145. SYNC~ Latency in ILAS Phase (Two-Lane Mode)
tim_sysref_subclass1_bas669.gifFigure 146. SYSREF Timing (Subclass 1)
tim_sync_subclass2_bas669.gifFigure 147. SYNC~ Timing (Subclass 2)