SBAS664B May   2014  – November 2014 ADC34J42 , ADC34J43 , ADC34J44 , ADC34J45

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Handling Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Summary of Special Mode Registers
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics: ADC34J44, ADC34J45
    7. 7.7  Electrical Characteristics: ADC34J42, ADC34J43
    8. 7.8  Electrical Characteristics: General
    9. 7.9  AC Performance: ADC34J45
    10. 7.10 AC Performance: ADC34J44
    11. 7.11 AC Performance: ADC34J43
    12. 7.12 AC Performance: ADC34J42
    13. 7.13 Digital Characteristics
    14. 7.14 Timing Characteristics
    15. 7.15 Typical Characteristics: ADC34J45
    16. 7.16 Typical Characteristics: ADC34J44
    17. 7.17 Typical Characteristics: ADC34J43
    18. 7.18 Typical Characteristics: ADC34J42
    19. 7.19 Typical Characteristics: Common Plots
    20. 7.20 Typical Characteristics: Contour Plots
  8. 8 Parameter Measurement Information
    1. 8.1 Timing Diagrams
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Inputs
      2. 9.3.2 Clock Input
        1. 9.3.2.1 SNR and Clock Jitter
        2. 9.3.2.2 Input Clock Divider
      3. 9.3.3 Power-Down Control
      4. 9.3.4 Internal Dither Algorithm
      5. 9.3.5 JESD204B Interface
        1. 9.3.5.1 JESD204B Initial Lane Alignment (ILA)
        2. 9.3.5.2 JESD204B Test Patterns
        3. 9.3.5.3 JESD204B Frame Assembly
        4. 9.3.5.4 Digital Outputs
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Gain
      2. 9.4.2 Overrange Indication
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Register Initialization
          1. 9.5.1.1.1 Serial Register Write
          2. 9.5.1.1.2 Serial Register Readout
      2. 9.5.2 Register Initialization
      3. 9.5.3 Start-Up Sequence
    6. 9.6 Register Map
      1. 9.6.1 Serial Register Description
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Driving Circuit Design: Low Input Frequencies
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Driving Circuit Design: Input Frequencies Between 100 MHz to 230 MHz
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
      3. 10.2.3 Driving Circuit Design: Input Frequencies Greater than 230 MHz
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curve
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGZ Package
VQFN-48
(Top View)
PO_BAS664.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AVDD 4, 5, 8, 9, 12, 17, 20, 25, 28, 29, 32, 39, 46 I Analog 1.8-V power supply
CLKM 18 I Negative differential clock input for the ADC
CLKP 19 I Positive differential clock input for the ADC
DAM 48 O Negative serial JESD204B output for channel A
DAP 47 O Positive serial JESD204B output for channel A
DBM 45 O Negative serial JESD204B output for channel B
DBP 44 O Positive serial JESD204B output for channel B
DCM 41 O Negative serial JESD204B output for channel C
DCP 40 O Positive serial JESD204B output for channel C
DDM 38 O Negative serial JESD204B output for channel D
DDP 37 O Positive serial JESD204B output for channel D
DVDD 3, 34 I Digital 1.8-V power supply
GND PowerPAD™ I Ground, 0 V
INAM 6 I Negative differential analog input for channel A
INAP 7 I Positive differential analog input for channel A
INBM 11 I Negative differential analog input for channel B
INBP 10 I Positive differential analog input for channel B
INCM 26 I Negative differential analog input for channel C
INCP 27 I Positive differential analog input for channel C
INDM 31 I Negative differential analog input for channel D
INDP 30 I Positive differential analog input for channel D
OVRA 2 O Overrange indicator for channel A
OVRB 1 O Overrange indicator for channel B
OVRC 36 O Overrange indicator for channel C
OVRD 35 O Overrange indicator for channel D
PDN 33 I Power-down control. This pin has an internal 150-kΩ pull-down resistor.
RESET 21 I Hardware reset; active high. This pin has an internal 150-kΩ, pull-down resistor.
SCLK 13 I Serial interface clock input. This pin has an internal 150-kΩ pull-down resistor.
SDATA 14 I Serial interface data input. This pin has an internal 150-kΩ pull-down resistor.
SDOUT 16 O Serial interface data output
SEN 15 I Serial interface enable. Active low.
This pin has an internal 150-kΩ pull-up resistor to AVDD.
SYNCM~ 42 I Negative JESD204B synch input
SYNCP~ 43 I Positive JESD204B synch input
SYSREFM 23 I Negative external SYSREF input
SYSREFP 22 I Positive external SYSREF input
VCM 24 O Common-mode voltage output for the analog inputs