JAJSNQ4 March   2023 ADC34RF52

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 7.3.5.5 NCO Frequency programming using the SPI interface
        6. 7.3.5.6 Fast Frequency Hopping
          1. 7.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
          1. 7.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 7.3.6.2.3 JESD204B Frame Assembly with Decimation - Single Band
          4. 7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 7.3.6.3 SERDES Output MUX
      7. 7.3.7 Test Pattern
        1. 7.3.7.1 Transport Layer
        2. 7.3.7.2 Link Layer
        3. 7.3.7.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Mode
      2. 7.4.2 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband RF Sampling Receiver
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 Step 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.4 ADC Foreground Calibration

The internal ADC architecture is sensitive to temperature changes. The ADC34RF52 contains two additional internal ADC cores (one for channel A/B and one for channel C/D) which are used whenever one of the ADCs is in calibration. ADCs are calibrated as pairs where one ADC at a time is connected to the internal calibration DAC. The calibration is configured via SPI register writes and can be executed using SPI register writes or using the GPIO1 pin. When executed the calibration takes ~ 27 ms/ADC pair (~13.5 ms/ADC). The example in Figure 7-15shows 2x internal averaging where 4 ADC cores (#1,2,3,4 for chA/B and #6,7,8,9 for chC/D) are used in operation and ADCs #5 and #10 for calibration.

GUID-C321E399-F349-4A58-BFD2-1131FDCCB06D-low.svgFigure 7-15 Internal ADC setup for 2x averaging mode