JAJSNQ4 March 2023 ADC34RF52
PRODUCTION DATA
Figure 7-16 shows a timing diagram of the calibration control using GPIO1 pin.
When GPIO1 transitions to LOW logic state:
If GPIO1 is being held low when the calibration of an ADC pair is completed, the next ADC pair is switched and a new calibration is triggered. The order in which ADC pair gets calibrated can be configured via SPI to serial or random.
When using 2x averaging for example, the calibration must be executed for 5 ADC pairs to make sure all ADCs in use have been calibrated recently.
Figure 7-17 shows the ADC switch happens approximately 120 ns after the logic level change on GPIO1 is detected.