JAJSNQ4 March   2023 ADC34RF52

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 7.3.5.5 NCO Frequency programming using the SPI interface
        6. 7.3.5.6 Fast Frequency Hopping
          1. 7.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
          1. 7.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 7.3.6.2.3 JESD204B Frame Assembly with Decimation - Single Band
          4. 7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 7.3.6.3 SERDES Output MUX
      7. 7.3.7 Test Pattern
        1. 7.3.7.1 Transport Layer
        2. 7.3.7.2 Link Layer
        3. 7.3.7.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Mode
      2. 7.4.2 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband RF Sampling Receiver
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 Step 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.1.4 Analog out-of-band dither

The ADC34RF52 provides optional (enabled via SPI writes) analog out-of-band, large amplitude dither. It has a bandwidth of ~ 20 MHz located at DC and an adjustable amplitude with a maximum dither power of approximately ~ -20 dBFS (PAR ~ 9 dB). The dither is completely rolled-off into the noise floor within ~ 100 MHz as illustrated in Figure 7-5. Since the dither is large, the amplitude is recommended for the signal input not to exceed -2.5 dBFS to avoid input saturation. The dither signal also couples to the input signal and, depending on input frequency, can degrade the close in phase noise for offsets > 1 MHz.

GUID-C19454BE-FD67-4F4D-85CC-87178C9F56A9-low.gifFigure 7-5 Analog out-of-band dither

In the frequency domain, the dither signal shows up in individual tones as shown in Figure 7-9. The dither update frequency can be adjusted with the dither divider setting. The dither update frequency is: FS / 4 / 2047 / 'Dither Divider'. In the frequency spectrum, there is a 2 larger dither spurs at FIN +/- FS / 4 / 'Dither Divider'.

By default, the divider is set to 50, which translates to a dither spur spacing of ~ 7 kHz. A divider setting of 32 translates to a dither spacing of ~ 11 kHz as shown in Figure 7-7. The lower the divider setting, the higher the dither tone frequency. Figure 7-7 also shows that the dither energy reduces as the offset frequency increases. Less dither energy reduces the higher harmonic spur improvement.

GUID-20221209-SS0I-D4SV-WGTQ-RF8SGJDHHVPW-low.svgFigure 7-6 Dither Close-Up
GUID-20221209-SS0I-XG55-CHRJ-3BD0QXPLZXQK-low.svgFigure 7-7 Dither vs Dither Divider Setting

The analog dither must be enabled in multiple locations. The different dither amplitudes must be used based on the internal averaging as shown in Table 7-5.

Table 7-5 Recommended dither amplitude settings
ModeAmplitudeDither Amp1Dither Amp2
1x AVG±1024 codes00
1x AVG±768 codes0-4
2x AVG±1024 codes30
2x AVG±768 codes00

The internal analog dither can be enabled via the following register writes. After enabling the dither (or changing the dither amplitude) another calibration needs to be performed. See Table 7-9.

Table 7-6 Register write example for configuring the internal dither
ADDRDATADESCRIPTIONADDRDATADESCRIPTION
0x050x40Select ANALOG page0xB10x00Sets dither divider. 0x00 = /50
0xA80x00DITHER AMP1: 3 = 0x80, 0 = 0x000xB20x00
0xCD0x00DITHER AMP2: -4 = 0x40, 0 = 0x000xAF0x18
0x040x010xAF0x100x10 = dither ENABLED, 0x90 = dither DISABLED
0x200x040x040x01
0x910x400x200x00
0xAF0x100x040x00