JAJSNQ4 March 2023 ADC34RF52
PRODUCTION DATA
The ADC34RF52 provides several different options to output test patterns instead of the actual output data of the ADC to simplify the serial interface and system debug of the JESD204B digital interface link. The output data path is shown in Figure 7-41.
The available test patterns in each block are described in Table 7-41. Both test pattern blocks replace output data from the digital block (and not from the ADC); therefore, are available in decimation or decimation bypass mode.
TEST PATTERN LOCATION | TYPE | 8b/10b encoded | REGISTER PAGE | REGISTER |
---|---|---|---|---|
TRANSPORT LAYER | CUSTOM PATTERN | Yes | JESD 0x05 0x04 | 0x2E, D0 |
TOGGLE 1010 PATTERN | Yes | 0x2E, D1 | ||
RAMP PATTERN | Yes | 0x2E, D2 | ||
PRBS PATTERN (27.. 231) | Yes | 0x2F, D0 | ||
LINK LAYER | JESD204B TEST PATTERNS | Depends | 0x2D, D2-D0 | |
PRBS PATTERN (27.. 231) | No | 0x2F, D4 |
The RAMP pattern provides two different output options. Internally each ADC data bus consists of 4 parallel data streams (1 stream per serdes lane). The RAMP pattern is generated for each stream and a different starting value can be set for each stream. By default the starting values are 0. For example a LMFS mode using 2 lanes/ADC would show a slow ramp which increments once every 2 clock cycles with starting values set to 0 and ramp increment = 1. Also, a RAMP pattern which increments every clock cycle can be set using different starting values (that is, 0/1) for the 2 streams/lanes and setting the RAMP increment to 2. Table 7-42 shows how to enable the RAMP test pattern.
ADDR | DATA | DESCRIPTION |
---|---|---|
0x05 | 0x04 | Select JESD page |
0x32 | 0x01 | Set lane DOUT1 starting value = 1 |
0x36 | 0x03 | Set lane DOUT3 starting value = 1 |
0x42 | 0x01 | Set lane DOUT5 starting value = 1 |
0x46 | 0x03 | Set lane DOUT7 starting value = 1 |
0x2E | 0x14 | Enable RAMP pattern, RAMP increment = 2 |