JAJSNQ4 March   2023 ADC34RF52

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (Dither DISABLED)
    8. 6.8  Electrical Characteristics - AC Specifications (Dither ENABLED)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
        1. 7.3.1.1 Input Bandwidth and Full-Scale
        2. 7.3.1.2 Input Imbalance
        3. 7.3.1.3 Overrange Indication
        4. 7.3.1.4 Analog out-of-band dither
      2. 7.3.2 Sampling Clock Input
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Capture Detection
      4. 7.3.4 ADC Foreground Calibration
        1. 7.3.4.1 Calibration Control
        2. 7.3.4.2 ADC Switch
        3. 7.3.4.3 Calibration Configuration
      5. 7.3.5 Decimation Filter
        1. 7.3.5.1 Decimation Filter Response
        2. 7.3.5.2 Decimation Filter Configuration
        3. 7.3.5.3 20-bit Output Mode
        4. 7.3.5.4 Numerically Controlled Oscillator (NCO)
        5. 7.3.5.5 NCO Frequency programming using the SPI interface
        6. 7.3.5.6 Fast Frequency Hopping
          1. 7.3.5.6.1 Fast frequency hopping using the GPIO1/2 pins
          2. 7.3.5.6.2 Fast frequency hopping using GPIO1/2, SEN and SDATA pins
          3. 7.3.5.6.3 Fast frequency hopping using the fast SPI
      6. 7.3.6 JESD204B Interface
        1. 7.3.6.1 JESD204B Initial Lane Alignment (ILA)
          1. 7.3.6.1.1 SYNC Signal
        2. 7.3.6.2 JESD204B Frame Assembly
          1. 7.3.6.2.1 JESD204B Frame Assembly in Bypass Mode
          2. 7.3.6.2.2 JESD204B Frame Assembly with Real Decimation - Single Band
          3. 7.3.6.2.3 JESD204B Frame Assembly with Decimation - Single Band
          4. 7.3.6.2.4 JESD204B Frame Assembly with Decimation - Dual Band
        3. 7.3.6.3 SERDES Output MUX
      7. 7.3.7 Test Pattern
        1. 7.3.7.1 Transport Layer
        2. 7.3.7.2 Link Layer
        3. 7.3.7.3 Internal Capture Memory Buffer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Bypass Mode
      2. 7.4.2 Digital Averaging
    5. 7.5 Programming
      1. 7.5.1 GPIO Pin Control
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
    6. 7.6 Register Maps
      1. 7.6.1 Detailed Register Description
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Wideband RF Sampling Receiver
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Clocking
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Sampling Clock
      4. 8.2.4 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Initial Device Configuration After Power-Up
        1. 8.3.1.1  STEP 1: RESET
        2. 8.3.1.2  STEP 2: Device Configuration
        3. 8.3.1.3  STEP 3: JESD Interface Configuration (1)
        4. 8.3.1.4  STEP 4: SYSREF Synchronization
        5. 8.3.1.5  STEP 5: JESD Interface Configuration (2)
        6. 8.3.1.6  STEP 6: Analog Trim Settings
        7. 8.3.1.7  STEP 7: Calibration Configuration
        8. 8.3.1.8  STEP 8: SYSREF Synchronization
        9. 8.3.1.9  STEP 9: Run Power up Calibration
        10. 8.3.1.10 Step 10: JESD Interface Synchronization
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics - AC Specifications (Dither DISABLED)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 1.5 GSPS, Bypass mode, 50% clock duty cycle, AVDD18 = 1.8 V, AVDD12, CLKVDD, DVDD = 1.2 V, –1-dBFS differential input and dither DISABLED, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NSD Noise Spectral Density fIN = 900 MHz, AIN = -20 dBFS
no averaging		 -153.3 dBFS/Hz
fIN = 900 MHz, AIN = -20 dBFS
2x averaging		 -156.1
NF Noise Figure fIN = 900 MHz, AIN = -20 dBFS
no averaging		 21.7 dB
fIN = 900 MHz, AIN = -20 dBFS
2x averaging		 19.7
SNR Signal-to-noise ratio
no averaging		 fIN = 100 MHz 64.1 dBFS
fIN = 600 MHz 64.1
fIN = 900 MHz 63.9
fIN = 900 MHz, Ain = -20 dBFS 65.1
fIN = 1.4 GHz 63.6
Signal-to-noise ratio
2x averaging		 fIN = 100 MHz 66.5
fIN = 600 MHz 66.6
fIN = 900 MHz 66.3
fIN = 900 MHz, Ain = -20 dBFS 67.9
fIN = 1.4 GHz 65.9
SINAD Signal to noise and distortion ratio fIN = 100 MHz 60.6 dBFS
fIN = 600 MHz 62.2
fIN = 900 MHz 62.1
fIN = 900 MHz, Ain = -20 dBFS 61.4
fIN = 1.4 GHz 62.0
ENOB Effective number of bits fIN = 100 MHz 10.4 Bits
fIN = 600 MHz 10.4
fIN = 900 MHz 10.3
fIN = 900 MHz, Ain = -20 dBFS 10.5
fIN = 1.4 GHz 10.3
THD Total Harmonic Distortion (First five harmonics) fIN = 100 MHz 64 dBc
fIN = 600 MHz 67
fIN = 900 MHz 67
fIN = 900 MHz, Ain = -20 dBFS 64
fIN = 1.4 GHz 68
HD2 Second Harmonic Distortion fIN = 100 MHz 72 dBc
fIN = 600 MHz 70
fIN = 900 MHz 71
fIN = 900 MHz, Ain = -20 dBFS 68
fIN = 1.4 GHz 69
HD3 Third Harmonic Distortion fIN = 100 MHz 65 dBc
fIN = 600 MHz 73
fIN = 900 MHz 71
fIN = 900 MHz, Ain = -20 dBFS 69
fIN = 1.4 GHz 81
Non HD2,3 Spur free dynamic range (excluding HD2 and HD3) fIN = 100 MHz 82 dBFS
fIN = 600 MHz 83
fIN = 900 MHz 83
fIN = 900 MHz, Ain = -20 dBFS 93
fIN = 1.4 GHz 81
IMD3 Two tone inter-modulation distortion f1 = 900 MHz, f2 = 1000 MHz, AIN = -7 dBFS/tone 81 dBFS