JAJSPH5 December   2022 ADC3544

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 Digital Filter Operation
        2. 8.3.4.2 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Sampling Clock
        3. 9.2.2.3 Voltage Reference
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Register Initialization During Operation
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Trademarks
    3. 10.3 静電気放電に関する注意事項
    4. 10.4 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 RSB Package, 40-Pin WQFN
(Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
INPUT/REFERENCE
AINM 14 I Negative analog input
AINP 13 I Positive analog input
REFBUF 4 I 1.2-V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions.
REFGND 3 I Reference ground input, 0 V
VCM 9 O Common-mode voltage output for the analog inputs, 0.95 V
VREF 2 I External voltage reference input, 1.6 V.
CLOCK
CLKM 7 I Negative differential sampling clock input for the ADC
CLKP 6 I Positive differential sampling clock input for the ADC
CONFIGURATION
NC 18 - Do not connect
PDN/SYNC 1 I Power down, synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor.
RESET 10 I Hardware reset; active high. This pin has an internal 21 kΩ pull-down resistor.
SCLK 40 I Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO 39 I Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
SEN 17 I Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
DIGITAL INTERFACE
D0 38 O CMOS output used with 16 bit output (configured via output bit formatter). This becomes LSB. When not used can be left unconnected.
D1 37 O CMOS output used with 16 bit output (configured via output bit formatter). This becomes LSB-1. When not used can be left unconnected.
D2 36 O CMOS output for data bit D0.
D3 35 I/O CMOS output for data bit D1. Used as DCLKIN in serial CMOS output modes.
D4 34 O CMOS output for data bit D2.
D5 33 O CMOS output for data bit D3.
D6 32 O CMOS output for data bit D4.
D7 30 O CMOS output for data bit D5.
D8 29 O CMOS output for data bit D6.
D9 28 O CMOS output for data bit D7.
D10 27 O CMOS output for data bit D8.
D11 24 O CMOS output for data bit D9. Lane 0 in serial CMOS output mode.
D12 23 O CMOS output for data bit D10. Lane 1 in serial CMOS output mode.
D13 22 O CMOS output for data bit D11.
D14 21 O CMOS output for data bit D12.
D15 20 O CMOS output for data bit D13 (MSB).
DCLK 26 O CMOS output for data bit clock
FCLK 19 O Frame clock output in serial CMOS output mode.
POWER SUPPLY
AVDD 5,8,11,16 I Analog 1.8-V power supply
GND 12,15 I Ground, 0 V
IOGND 25 I Ground, 0 V for digital interface
IOVDD 31 I 1.8-V power supply for digital interface
PowerPAD™ -- -- Connect to ground