JAJSPH5 December   2022 ADC3544

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 Digital Filter Operation
        2. 8.3.4.2 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS Interface
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Sampling Clock
        3. 9.2.2.3 Voltage Reference
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Set Up
      1. 9.3.1 Register Initialization During Operation
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Trademarks
    3. 10.3 静電気放電に関する注意事項
    4. 10.4 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.5.5 Output Bit Mapper

The output bit mapper allows to change the output bit order for any selected interface mode.

Figure 8-36 Output Bit Mapper

There is a two step process to change the output bit mapping and assemble the output data bus:

  1. In parallel interface mode, the maximum output resolution is 18-bit, in serial interface mode the maximum output resolution is 20-bit. Each output bit of either channel has a unique identifier bit as shown in the Table 8-9. The MSB starts with bit D19. Depending on output resolution chosen, the LSB is D6 (14-bit) to D0 (20-bit). The previous sample is only needed in 2-w mode.
  2. The bit mapper is then used to assemble the output sample. The following sections detail how to remap both a parallel and a serial output format.

Table 8-9 Unique identifier of each data bit
Bit Previous sample (2w only) Current sample
D19 (MSB) 0x2D 0x6D
D18 0x2C 0x6C
D17 0x27 0x67
D16 0x26 0x66
D15 0x25 0x65
D14 0x24 0x64
D13 0x1F 0x5F
D12 0x1E 0x5E
D11 0x1D 0x5D
D10 0x1C 0x5C
D9 0x17 0x57
D8 0x16 0x56
D7 0x15 0x55
D6 0x14 0x54
D5 0x0F 0x4F
D4 0x0E 0x4E
D3 0x0D 0x4D
D2 0x0C 0x4C
D1 0x07 0x47
D0 (LSB) 0x06 0x46

In parallel SDR mode, a data bit (with unique identifier) needs to be assigned to each output pin using the register addresses as shown in Figure 8-37. The example on the right shows the output data bus reversed to where the MSB starts on pin D2 instead of pin D15.

Figure 8-37 SDR output mapping (left) and example (right)

In parallel DDR mode, a data bit (with unique identifier) needs to be assigned to each output pin for both the rising and the falling edge of the DCLK using the register addresses as shown in Figure 8-38. D9 and D10 are used for 16 and 18-bit output. The example on the right shows the output data bus remapped to where the MSB starts on D17 instead of D11.

Figure 8-38 DDR output timing diagram with output mapping (left) and example (right)

In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the serial output stream. There are a total of 40 addresses (0x39 to 0x60). When using complex decimation, the output bit mapper is applied to both the “I” and the “Q” sample.

2-wire mode: in this mode, both the current and the previous sample have to be used in the address space as shown in Figure 8-39. The address order is different for 14/18-bit and 16/20-bit. Note: there are unused addresses between samples for resolution less than 20-bit (grey back ground), which can be skipped if not used.

Figure 8-39 2-wire output bit mapper

In the following example (Figure 8-40), the 16-bit 2-wire serial output is reordered to where pin D12 carries the 8 MSB and pin D11 carries 8 LSBs.

Figure 8-40 Example: 2-wire output mapping

1-wire mode: Only the ‘current’ sample needs to programmed in the address space.

Figure 8-41 1-wire output bit mapping