JAJSL75B February   2021  – October 2022 ADC3561 , ADC3562 , ADC3563

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  絶対最大定格
    2. 6.2  ESD 定格
    3. 6.3  推奨動作条件
    4. 6.4  熱に関する情報
    5. 6.5  電気的特性 - 消費電力
    6. 6.6  電気的特性 - DC 仕様
    7. 6.7  電気的特性 - AC 仕様
    8. 6.8  タイミング要件
    9. 6.9  Typical Characteristics - ADC3561
    10. 6.10 Typical Characteristics - ADC3562
    11. 6.11 Typical Characteristics - ADC3563
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX for Dual Band Decimation
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Output Formatter
        2. 8.3.5.2 Output Bit Mapper
        3. 8.3.5.3 Output Scrambler
        4. 8.3.5.4 Output Interface/Mode Configuration
          1. 8.3.5.4.1 Configuration Example
        5. 8.3.5.5 Output Data Format
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Documentation Support
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 サポート・リソース
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-AD4231C7-5FBF-464C-A970-156DD4C83F82-low.gif Figure 5-1 RSB (WQFN) Package, 40-Pin
(Top View)
Table 5-1 Pin Descriptions
PIN TYPE DESCRIPTION
NAME NO.
INPUT/REFERENCE
AINP 12 I Positive analog input
AINM 13 I Negative analog input
VCM 8 O Common-mode voltage output for the analog inputs, 0.95 V
VREF 2 I External voltage reference input, 1.6 V
REFBUF 4 I 1.2V external voltage reference input for use with internal reference buffer
REFGND 3 I Reference ground input, 0 V
CLOCK
CLKM 7 I Negative differential sampling clock input for the ADC
CLKP 6 I Positive differential sampling clock input for the ADC
CONFIGURATION
PDN/SYNC 1 I Power down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor.
RESET 9 I Hardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor.
SEN 16 I Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
SCLK 35 I Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO 10 I Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
NC 27,38,39 - Do not connect
DIGITAL INTERFACE
DA0P 20 O Positive differential serial LVDS output for lane 0, channel A
DA0M 19 O Negative differential serial LVDS output for lane 0, channel A
DA1P 18 O Positive differential serial LVDS output for lane 1, channel A
DA1M 17 O Negative differential serial LVDS output for lane 1, channel A
DB0P 31 O Positive differential serial LVDS output for lane 0, channel B.
Used only in dual band complex decimation. Default is powered down.
DB0M 32 O Negative differential serial LVDS output for lane 0, channel B.
Used only in dual band complex decimation. Default is powered down.
DB1P 33 O Positive differential serial LVDS output for lane 1, channel B.
Used only in dual band complex decimation. Default is powered down.
DB1M 34 O Negative differential serial LVDS output for lane 1, channel B.
Used only in dual band complex decimation. Default is powered down.
DCLKP 23 O Positive differential serial LVDS bit clock output.
DCLKM 22 O Negative differential serial LVDS bit clock output.
FCLKP 28 O Positive differential serial LVDS frame clock output.
FCLKM 29 O Negative differential serial LVDS frame clock output.
DCLKINP 25 I Positive differential serial LVDS bit clock input.
DCLKINM 24 I Negative differential serial LVDS bit clock input.
POWER SUPPLY
AVDD 5,15,36 I Analog 1.8-V power supply
GND 11,14,37,40, PowerPad I Ground, 0 V
IOGND 26 I Ground, 0 V for digital interface
IOVDD 21,30 I 1.8-V power supply for digital interface