JAJSK68A October   2020  – May 2022 ADC3641 , ADC3642 , ADC3643

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications ADC3641
    8. 6.8  Electrical Characteristics - AC Specifications ADC3642
    9. 6.9  Electrical Characteristics - AC Specifications ADC3643
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics - ADC3641
    12. 6.12 Typical Characteristics - ADC3642
    13. 6.13 Typical Characteristics - ADC3643
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
          1. 8.3.4.2.1 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.4.4 Decimation Filter

The ADC364x supports complex decimation by 2, 4, 8, 16 and 32 with a pass-band bandwidth of ~ 80% and a stopband rejection of at least 85dB. Table 8-3 gives an overview of the pass-band bandwidth of the different decimation settings with respect to ADC sampling rate FS. In real decimation mode the output bandwidth is half of the complex bandwidth.

Table 8-3 Decimation Filter Summary and Maximum Available Output Bandwidth
REAL/COMPLEX DECIMATIONDECIMATION SETTING NOUTPUT RATEOUTPUT BANDWIDTHOUTPUT RATE
(FS = 65 MSPS)		OUTPUT BANDWIDTH
(FS = 65 MSPS)
Complex2FS / 2 complex0.8 × FS / 232.5 MSPS complex26 MHz
4FS / 4 complex0.8 × FS / 416.25 MSPS complex13 MHz
8FS / 8 complex0.8 × FS / 88.125 MSPS complex6.5 MHz
16FS / 16 complex0.8 × FS / 164.0625 MSPS complex3.25 MHz
32FS / 32 complex0.8 × FS / 322.03125 MSPS complex1.625 MHz
Real2FS / 2 real0.4 × FS / 232.5 MSPS13 MHz
4FS / 4 real0.4 × FS / 416.25 MSPS6.5 MHz
8FS / 8 real0.4 × FS / 88.125 MSPS3.25 MHz
16FS / 16 real0.4 × FS / 164.0625 MSPS1.625 MHz
32FS / 32 real0.4 × FS / 322.03125 MSPS0.8125 MHz

The decimation filter responses normalized tot he ADC sampling clock frequency are illustrated in . They are interpreted as follows:

Each figure contains the filter pass-band, transition band(s) and alias or stop-band(s) as shown in Figure 8-26 to Figure 8-35. The x-axis shows the offset frequency (after the NCO frequency shift) normalized to the ADC sampling rate FS.

For example, in the divide-by-4 complex setup, the output data rate is FS / 4 complex with a Nyquist zone of FS / 8 or 0.125 × FS. The transition band is centered around 0.125 × FS and the alias transition band is centered at 0.375 × FS (colored in blue). The stop-bands, which alias on top of the pass-band, are centered at 0.25 × FS and 0.5 × FS and are colored in red. The stop-band attenuation is greater than 85 dB.

GUID-F534D2B6-78DE-4221-89AD-D9EE40F7F60D-low.gifFigure 8-25 Interpretation of the Decimation Filter Plots
GUID-D95AC7A3-5B38-4F18-BDEC-E9BAFE1306AF-low.gifFigure 8-26 Decimation by 2 complex frequency response
GUID-DE255B91-352C-4BF2-923E-86C0CCA79588-low.gifFigure 8-28 Decimation by 4 complex frequency response
GUID-AF4113F0-A870-4DF8-B5A8-ED1F4554290E-low.gifFigure 8-30 Decimation by 8 complex frequency response
GUID-BD54C41E-7182-429A-814A-CB280F8D1ACA-low.gifFigure 8-32 Decimation by 16 complex frequency response
GUID-0269266F-3886-46CE-97CB-0A5EA229BE08-low.gifFigure 8-34 Decimation by 32 complex frequency response
GUID-413B0BEA-DB9A-449A-8FE3-143C781B9C13-low.gifFigure 8-27 Decimation by 2 complex passband ripple response
GUID-E87E9DFA-1F99-4C4B-94A6-4B513818A08B-low.gifFigure 8-29 Decimation by 4 complex passband ripple response
GUID-80589536-966D-4565-B96C-7E4E5890BA5E-low.gifFigure 8-31 Decimation by 8 complex passband ripple response
GUID-F4F7B173-AF84-40EA-9464-4726A375FE54-low.gifFigure 8-33 Decimation by 16 complex passband ripple response
GUID-61DB71EC-2315-4E56-9C48-A25763C0B28E-low.gifFigure 8-35 Decimation by 32 complex passband ripple response