JAJSK68A October   2020  – May 2022 ADC3641 , ADC3642 , ADC3643

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications ADC3641
    8. 6.8  Electrical Characteristics - AC Specifications ADC3642
    9. 6.9  Electrical Characteristics - AC Specifications ADC3643
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics - ADC3641
    12. 6.12 Typical Characteristics - ADC3642
    13. 6.13 Typical Characteristics - ADC3643
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
          1. 8.3.4.2.1 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-D9BAFB03-7116-4048-A551-19D7AAB630D8-low.gif Figure 5-1 RSB Package,40-Pin WQFN,Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
INPUT/REFERENCE
AINM 13 I Negative analog input, channel A
AINP 12 I Positive analog input, channel A
BINP 39 I Positive analog input, channel B
BINM 38 I Negative analog input, channel B
REFBUF 4 I 1.2 V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions.
REFGND 3 I Reference ground input, 0 V
VCM 8 O Common-mode voltage output for the analog inputs, 0.95 V
VREF 2 I External voltage reference input
CLOCK
CLKM 7 I Negative differential sampling clock input for the ADC
CLKP 6 I Positive differential sampling clock input for the ADC
CONFIGURATION
PDN/SYNC 1 I Power down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor.
RESET 9 I Hardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor.
SCLK 35 I Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO 10 I Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
SEN 16 I Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
DIGITAL INTERFACE
DA0 17 O CMOS digital data output.
DA1 18 I/O CMOS digital data output. Used as FCLK frame clock output for serialized CMOS output modes. Configured using SPI.
DA2 19 O CMOS digital data output.
DA3 20 O CMOS digital data output.
DA4 22 O CMOS digital data output.
DA5 23 O CMOS digital data output.
DA6 24 O CMOS digital data output.
DB0 34 O CMOS digital data output.
DB1 33 I/O CMOS digital data output. Used as DCLKIN bit clock input for serialized CMOS output modes. Configured using SPI.
DB2 32 O CMOS digital data output.
DB3 31 O CMOS digital data output.
DB4 29 O CMOS digital data output.
DB5 28 O CMOS digital data output.
DB6 27 O CMOS digital data output.
DCLK 25 O CMOS output for data bit clock.
POWER SUPPLY
AVDD 5,15,36 I Analog 1.8-V power supply
GND 11,14,37,40, PowerPAD I Ground, 0 V
IOGND 26 I Ground, 0 V for digital interface
IOVDD 21,30 I 1.8-V power supply for digital interface