JAJSK68A October   2020  – May 2022 ADC3641 , ADC3642 , ADC3643

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications ADC3641
    8. 6.8  Electrical Characteristics - AC Specifications ADC3642
    9. 6.9  Electrical Characteristics - AC Specifications ADC3643
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics - ADC3641
    12. 6.12 Typical Characteristics - ADC3642
    13. 6.13 Typical Characteristics - ADC3643
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
          1. 8.3.4.2.1 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.5.6 Output Interface/Mode Configuration

The following sequence summarizes all the relevant registers for changing the output interface and/or enabling the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining steps can come in any order.

Table 8-10 Configuration steps for changing interface or decimation
STEP FEATURE ADDRESS DESCRIPTION
1 Output Interface 0x07 Select the output interface bit mapping depending on resolution and output interface.
Output Resolution DDR 2-wire 1-wire 1/2-wire
14-bit 0xA9 0x2B 0x6C 0x8D
16-bit 0x4B
18-bit N/A 0x2B
20-bit N/A 0x4B
2 0x13 Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13 to 0x01, wait ~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00
3 0x0A/B/C When changing the output interface bit mapper (0x07), the CMOS output buffer register has to be configured again.
4 0x18 For serial CMOS modes, DCLKIN EN (D4) needs to be enabled.
5 0x19 In serial CMOS, configure the FCLK registers based on bypass/decimation and # of lanes used.
Bypass/Decimation SCMOS FCLK SRC
(D7)		 FCLK DIV
(D4)		 TOG FCLK
(D0)
Bypass/ Real Decimation 2-wire 0 1 0
1-wire 0 0 0
1/2-wire 0 0 0
Complex Decimation 2-wire 1 0 0
1-wire 1 0 0
1/2-wire 0 0 1
6 0x1B Select the output interface resolution using the bit mapper (D5-D3).
7 0x1F For serial CMOS modes, DCLKIN EN (D6) and DCLK OB EN (D4) need to be enabled.
8 0x20
0x21
0x22		 In serial CMOS, select the FCLK pattern for decimation for proper duty cycle output of the FCLK.
Decimation Output Resolution 2-wire 1-wire 1/2-wire
Real Decimation 14-bit use default 0xFE000 use default
16-bit 0xFF000
18-bit 0xFF800
20-bit 0xFFC00
Complex Decimation 14-bit 0xFFFFF 0xFFFFF
16-bit
18-bit
20-bit
9 0x39..0x60
0x61..0x88		 Change output bit mapping for chA and chB if desired. This works also with the default interface selection.
10 Decimation Filter 0x24 Enable the decimation filter
11 0x25 Configure the decimation filter
12 0x2A/B/C/D
0x31/2/3/4		 Program the NCO frequency for complex decimation (can be skipped for real decimation)
13 0x27
0x2E		 Configure the complex output data stream (set both bits to 0 for real decimation)
Serial CMOS OP-Order (D4) Q-Delay (D3)
2-wire 1 0
1-wire 0 1
1/2-wire 1 1
14 0x26 Set the mixer gain and toggle the mixer reset bit to update the NCO frequency.