JAJSK68A October   2020  – May 2022 ADC3641 , ADC3642 , ADC3643

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications ADC3641
    8. 6.8  Electrical Characteristics - AC Specifications ADC3642
    9. 6.9  Electrical Characteristics - AC Specifications ADC3643
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics - ADC3641
    12. 6.12 Typical Characteristics - ADC3642
    13. 6.13 Typical Characteristics - ADC3643
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
          1. 8.3.4.2.1 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.5.5 Output Bit Mapper

The output bit mapper allows to change the output bit order for any selected interface mode.

Figure 8-42 Output Bit Mapper

It is a two step process to change the output bit mapping and assemble the output data bus:

  1. Both channel A and B can have up to 20-bit output. Each output bit of either channel has a unique identifier bit as shown in the Table 8-9 below. The MSB starts with bit D19 – depending on output resolution chosen the LSB would be D6 (14-bit) to D0 (20-bit). The ‘previous sample’ is only needed in 2-w mode.
  2. The bit mapper is then used to assemble the output sample. The following sections detail how to remap both a parallel and a serial output format.

Table 8-9 Unique identifier of each data bit
Bit Channel A Channel B
Previous sample (2-w only) Current sample Previous sample (2-w only) Current sample
D19 (MSB) 0x2D 0x6D 0x29 0x69
D18 0x2C 0x6C 0x28 0x68
D17 0x27 0x67 0x23 0x63
D16 0x26 0x66 0x22 0x62
D15 0x25 0x65 0x21 0x61
D14 0x24 0x64 0x20 0x60
D13 0x1F 0x5F 0x1B 0x5B
D12 0x1E 0x5E 0x1A 0x5A
D11 0x1D 0x5D 0x19 0x59
D10 0x1C 0x5C 0x18 0x58
D9 0x17 0x57 0x13 0x53
D8 0x16 0x56 0x12 0x52
D7 0x15 0x55 0x11 0x51
D6 0x14 0x54 0x10 0x50
D5 0x0F 0x4F 0x0B 0x4B
D4 0x0E 0x4E 0x0A 0x4A
D3 0x0D 0x4D 0x09 0x49
D2 0x0C 0x4C 0x08 0x48
D1 0x07 0x47 0x03 0x43
D0 (LSB) 0x06 0x46 0x02 0x42

In parallel DDR mode, a data bit (with unique identifier) needs to be assigned to each output pin for both the rising and the falling edge of the DCLK using the register addresses as shown in Figure 8-43. The example on the right shows the output data bus remapped to where all 14 bit of channel A is output on DCLK rising edge followed by all 14 bit of channel B on DCLK falling edge.

Figure 8-43 DDR output timing diagram with output mapping (left) and example (right)

In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the serial output stream. There are a total of 40 addresses available per channel. Channel A spans from address 0x39 to 0x60 and channel B from address 0x61 to 0x88. When using complex decimation, the output bit mapper is applied to both the “I” and the “Q” sample.

2-wire mode: in this mode both the current and the previous sample have to be used in the address space as shown in Figure 8-44 below. The address order is different for 14/18-bit and 16/20-bit. Note: there are unused addresses between samples for resolution less than 20-bit (grey back ground), which can be skipped if not used.

Figure 8-44 2-wire output bit mapper

In the following example (Figure 8-45), the 16-bit 2-wire serial output is reordered to where lane DA5/DB5 carries the 8 MSB and lane DA6/DB6 carries 8 LSBs.

Figure 8-45 Example: 2-wire output mapping

1-wire mode: Only the ‘current’ sample needs to programmed in the address space. If desired, it can be duplicated on DA5/DB5 as well (using addresses shown below) in order to have a redundant output. Lane DA5/DB5 needs to be powered up in that case.

Figure 8-46 1-wire output bit mapping

½-wire mode: The output is only on lane DA6 and the sample order is programmed into the 40 addresses of chA (from 0x39 to 0x60). It covers 2 samples (one for chA, one for chB) as shown below.

Figure 8-47 1/2-wire output bit mapping