JAJSK68A October   2020  – May 2022 ADC3641 , ADC3642 , ADC3643

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications ADC3641
    8. 6.8  Electrical Characteristics - AC Specifications ADC3642
    9. 6.9  Electrical Characteristics - AC Specifications ADC3643
    10. 6.10 Timing Requirements
    11. 6.11 Typical Characteristics - ADC3641
    12. 6.12 Typical Characteristics - ADC3642
    13. 6.13 Typical Characteristics - ADC3643
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Single Ended Input
          3. 8.3.1.2.3 Analog Input Termination and DC Bias
            1. 8.3.1.2.3.1 AC-Coupling
            2. 8.3.1.2.3.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
          1. 8.3.4.2.1 FS/4 Mixing with Real Output
        3. 8.3.4.3 Numerically Controlled Oscillator (NCO) and Digital Mixer
        4. 8.3.4.4 Decimation Filter
        5. 8.3.4.5 SYNC
        6. 8.3.4.6 Output Formatting with Decimation
          1. 8.3.4.6.1 Parallel CMOS
          2. 8.3.4.6.2 Serialized CMOS
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Parallel CMOS Output
        2. 8.3.5.2 Serialized CMOS output
          1. 8.3.5.2.1 SDR Output Clocking
        3. 8.3.5.3 Output Data Format
        4. 8.3.5.4 Output Formatter
        5. 8.3.5.5 Output Bit Mapper
        6. 8.3.5.6 Output Interface/Mode Configuration
          1. 8.3.5.6.1 Configuration Example
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.12 Typical Characteristics - ADC3642

Typical values at TA = 25 °C, ADC sampling rate FS = 25 MSPS, AIN = –1 dBFS differential input, AVDD = IOVDD = 1.8 V, 65k FFT, external 1.6 V reference, 5 pF output load, unless otherwise noted.

GUID-20200710-SS0I-P5HP-JB3Z-7QNGZGGC93T2-low.gif
Figure 6-18 Single Tone FFT at FIN = 1.1 MHz
GUID-20200810-CA0I-P5FF-LJM9-DFXGGC8G654S-low.gif
AIN = -20 dBFS
Figure 6-20 Single Tone FFT at FIN = 10 MHz
AIN = -20 dBFS/tone
Figure 6-22 Two Tone FFT at FIN = 10, 12 MHz
Figure 6-24 ENOB vs Input Frequency
FIN = 1.1 MHz
Figure 6-26 AC Performance vs Sampling Rate
FIN = 1.1 MHz
Figure 6-28 AC Performance vs AVDD
FIN = 1.1 MHz
Figure 6-30 INL vs Code
Figure 6-32 DC Histogram
GUID-20201002-CA0I-W2XR-KSXS-DVRNLF63DVG6-low.gif

FIN = 1 MHz

Figure 6-34 Current vs Sampling Rate
GUID-20201002-CA0I-BCNJ-LN2J-BJBJH9CXQCHL-low.gif

DDR CMOS, FIN = 1 MHz

Figure 6-36 IIOVDD Current vs Load Capacitance
GUID-20200810-CA0I-SJNJ-R8R6-GFXWM9B1SS0Q-low.gif
Figure 6-19 Single Tone FFT at FIN = 10 MHz
AIN = -7 dBFS/tone
Figure 6-21 Two Tone FFT at FIN = 10, 12 MHz
Figure 6-23 AC Performance vs Input Frequency
FIN = 1.1 MHz
Figure 6-25 AC Performance vs Input Amplitude
Differential (Diff) clock, FIN = 1.1 MHz
Figure 6-27 AC Performance vs Clock Amplitude
FIN = 1.1 MHz
Figure 6-29 AC Performance vs VCM vs Temperature
GUID-20200710-SS0I-7SKX-TPSN-BWMJTWM2156P-low.gif
FIN = 1.1 MHz
Figure 6-31 DNL vs Code
Pulse Input = 1 MHz
Figure 6-33 Pulse Response
GUID-20201002-CA0I-0GSN-KL5V-W02ZFWBGHSZ5-low.gif

FIN = 1 MHz

Figure 6-35 IIOVDD Current vs Decimation