SBASAU8 December   2024 ADC3649

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications (ADC3648 - 250 MSPS)
    8. 6.8  Electrical Characteristics - AC Specifications (ADC3649 - 500 MSPS)
    9. 6.9  Timing Requirements
    10. 6.10 Typical Characteristics, ADC3648
    11. 6.11 Typical Characteristics, ADC3649
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
        1. 8.3.1.1 Nyquist Zone Selection
        2. 8.3.1.2 Analog Front End Design
      2. 8.3.2 Sampling Clock
      3. 8.3.3 Multi-Chip Synchronization
        1. 8.3.3.1 SYSREF Monitor
      4. 8.3.4 Time-Stamp
      5. 8.3.5 Overrange
      6. 8.3.6 External Voltage Reference
      7. 8.3.7 Digital Gain
      8. 8.3.8 Decimation Filter
        1. 8.3.8.1 Uncommon Decimation Ratios
        2. 8.3.8.2 Decimation Filter Response
        3. 8.3.8.3 Decimation Filter Configuration
        4. 8.3.8.4 Numerically Controlled Oscillator (NCO)
      9. 8.3.9 Digital Interface
        1. 8.3.9.1 Parallel LVDS
        2. 8.3.9.2 Serial LVDS (SLVDS) with Decimation
          1. 8.3.9.2.1 SLVDS - Status Bit Insertion
        3. 8.3.9.3 Output Data Format
        4. 8.3.9.4 32-bit Output Resolution
        5. 8.3.9.5 Output Scrambler
        6. 8.3.9.6 Output MUX
        7. 8.3.9.7 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low Latency Mode
      2. 8.4.2 Digital Channel Averaging
      3. 8.4.3 Power Down Mode
    5. 8.5 Programming
      1. 8.5.1 GPIO Programming
      2. 8.5.2 Register Write
      3. 8.5.3 Register Read
      4. 8.5.4 Device Programming
      5. 8.5.5 Register Map
      6. 8.5.6 Detailed Register Description
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Wideband Spectrum Analyzer
      2. 9.2.2 Design Requirements
        1. 9.2.2.1 Input Signal Path
        2. 9.2.2.2 Clocking
      3. 9.2.3 Detailed Design Procedure
        1. 9.2.3.1 Sampling Clock
      4. 9.2.4 Application Performance Plots
    3. 9.3 Initialization Set Up
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

Figure 5-1 RTD Package, 64 Pin VQFNP
(Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 16, 33 I Analog ground, 0V
AINM 19 I Channel A differential signal input, negative connection. The differential input has programmable internal termination (100Ω or 200Ω) and is self biased.
AINP 18 I Channel A differential signal input, positive connection.
AVDD12 15, 22, 34 I Analog 1.2V supply
AVDD18 17, 20, 29, 32 I Analog 1.8V supply
BINM 30 I Channel B differential signal input, negative connection. The differential input has programmable internal termination (100Ω or 200Ω) and is self biased.
BINP 31 I Channel B differential signal input, positive connection.
CLKGND 23, 26 I Clock ground, 0V
CLKP 24 I Device sampling clock differential input. AC coupling and terminating the clock signal externally for best AC performance is recommended. The differential input is self biased to the input common-mode voltage (0.75V).
CLKM 25 I
DCLKP 55 O Differential LVDS data bit clock output.
DCLKM 56 O
DGND 1, 48, 57 I Digital ground, 0V
DOUT0/FCLKM 37 O Differential LVDS data bit output lane 0. In decimation mode this pin turns to the differential SLVDS frame clock output.
DOUT0/FCLKP 38 O
DOUT1M 39 O Differential LVDS data bit output lane 1. Can be left floating and powered down via SPI if not used.
DOUT1P 40 O
DOUT2M 41 O Differential LVDS data bit output lane 2. Can be left floating and powered down via SPI if not used.
DOUT2P 42 O
DOUT3M 43 O Differential LVDS data bit output lane 3. Can be left floating and powered down via SPI if not used.
DOUT3P 44 O
DOUT4M 45 O Differential LVDS data bit output lane 4. Can be left floating and powered down via SPI if not used.
DOUT4P 46 O
DOUT5P 49 O Differential LVDS data bit output lane 5. Can be left floating and powered down via SPI if not used.
DOUT5M 50 O
DOUT6P 51 O Differential LVDS data bit output lane 6. Can be left floating and powered down via SPI if not used.
DOUT6M 52 O
DOUT7P 53 O Differential LVDS data bit output lane 7. Can be left floating and powered down via SPI if not used.
DOUT7M 54 O
DOUT8M 59 O Differential LVDS data bit output lane 8. Can be left floating and powered down via SPI if not used.
DOUT8P 60 O
DOUT9M 61 O Differential LVDS data bit output lane 9. Can be left floating and powered down via SPI if not used.
DOUT9P 62 O
DOUT10M 63 O Differential LVDS data bit output lane 10. Can be left floating and powered down via SPI if not used.
DOUT10P 64 O
DOUT11P 3 O Differential LVDS data bit output lane 11. Can be left floating and powered down via SPI if not used.
DOUT11M 4 O
DOUT12P 5 O Differential LVDS data bit output lane 12. Can be left floating and powered down via SPI if not used.
DOUT12M 6 O
DOUT13P 7 O Differential LVDS data bit output lane 13. Can be left floating and powered down via SPI if not used.
DOUT13M 8 O
DOUT14P 9 O Differential LVDS data bit output lane 14. Can be left floating and powered down via SPI if not used.
DOUT14M 10 O
DOUT15P 11 O Differential LVDS data bit output lane 15 (MSB). Can be left floating and powered down via SPI if not used.
DOUT15M 12 O
DVDD12 2, 47 I Digital 1.2V supply
DVDD18 58 I Digital 1.8V supply
GPIO0 27 I/O Synchronization or control input or status output. Can be left floating if not used.
GPIO1 28 I/O Control input or status output or external voltage reference (1.2V). Can be left floating if not used.
RESET 35 I Hardware reset. Active high. This pin has an internal 21kΩ pull-down resistor to DGND.
SCLK 13 I Serial interface clock for the serial interface programming. This pin has an internal 21kΩ pull-down resistor to DGND.
SDIO 36 I/O Serial interface data input/output. This pin has an internal 21kΩ pull-down resistor to DGND.
SEN 14 I Serial interface chip select. This pin has an internal 21kΩ pull-up resistor to DVDD18.
VCM 21 O Common mode voltage output (1.4V)
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.