After power-up, the internal registers must be
initialized to the default values through a
hardware reset by applying a high pulse on the
RESET pin, as shown in Figure 9-8.
- Apply 1.2V DVDD12 digital power supply
- Apply 1.2V AVDD12 analog power supply
- Apply 1.8V power supplies (AVDD18, DVDD18), in no specific order
- Apply external voltage reference
(optional)
- Apply external sampling
clock
- Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses.
- Read back 'CFG RDY register'
(0x25, D4) to check if internal load is complete (< 10k clock cycles).
- If needed, begin programming the internal registers using the SPI.
- Full ADC performance is available after approximately 5M clock cycles.
Table 9-2 Power-Up Timing | MIN | TYP | MAX | UNIT |
t1 |
Power-on delay: delay from power up to active high RESET
pulse |
1 |
|
|
us |
t2 | Reset pulse width: active high RESET pulse width | 100 | | | ns |