SBASAP7 December 2024 ADC3664-SP
PRODUCTION DATA
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The device has a set of internal registers that can be accessed via SPI formed by the SEN (serial interface enable), SCLK (serial interface clock) and SDIO (serial interface data input/output) pins. Bits are serially shifted into the device when SEN is low. Input data is latched at every SCLK rising edge when SEN is active (low). The serial data is loaded into the register at the 24th SCLK rising edge when SEN is low. When the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20MHz down to as slow as a few hertz.