SBASAP7 December 2024 ADC3664-SP
PRODUCTION DATA
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In 2-wire mode, both the current sample and the previous sample columns of Table 7-3 are used. Furthermore, each BIT_ID for the current and previous sample in Table 7-3 needs to be mapped to a specific address which indicates the position of the bit in the respective lane. The address space order is different for 14-bit/18-bit resolutions and 16-bit/20-bit resolutions. The bit mapper address space is also different for each lane.
Figure 7-12 and Figure 7-13 show register addresses that correspond to the bit positions for each resolution setting and lane. The default values shown for each address are after configuring the ADC3664-SP into the 2-wire interface mode.
Figure 7-14 shows how the bit mapper can be configured to support 16-bit scrambled output. The bit mapper is configured so that the top and bottom halves of the samples are sent on separate lanes and the bits are sent out LSB first as described in Section 7.3.4.4.