SBASAP7 December 2024 ADC3664-SP
PRODUCTION DATA
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DCLKIN is an external clock to the ADC3664-SP where a delayed version of this clock is used as the output interface clock (DCLK). DCLKIN can be configured for external or internal biasing to a 1.2V common-mode voltage via SPI (D5 of 0x244). DCLKIN also has an internal 100Ω termination resistor.
Given the low latency architecture of the ADC3664-SP, the relationship between the sample clock (CLK) and DCLKIN needs to be controlled. DCLKIN and CLK must be phase locked to the same reference frequency. The falling edges of CLK and DCLKIN need to be 2.5ns apart otherwise a timing violation occurs. If a timing violation is observed, an internal timing violation detection circuit adds a 1ns delay between CLK and DCLKIN. The effect of this detection circuit is observed as a change in the tPD specification by one DCLK cycle.