The
ADC3664-SP
uses a serial LVDS (SLVDS) interface to output the ADCs' data which minimizes the number of
digital interconnects. The SLVDS interface can be configured to one of the following modes:
two LVDS lanes per channel (2-wire), one LVDS lane per channel (1-wire), or a half-lane mode
(1/2-wire) option where both channels are multiplexed on a single LVDS lane. The device
supports configurable output resolutions from 14-bit to 20-bit.
The ADC3664-SP
requires an external interface clock (DCLKIN). A delayed version of DCLKIN is used as the
interface output clock (DCLK).