SBASAP7 December   2024 ADC3664-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Input Bandwidth
        2. 7.3.1.2 Analog Front End Design
          1. 7.3.1.2.1 Sampling Glitch Filter
          2. 7.3.1.2.2 AC Coupling
          3. 7.3.1.2.3 DC Coupling
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Differential Vs Single-ended Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference
      4. 7.3.4 Digital Data Path & Interface
        1. 7.3.4.1 Data Path Overview
        2. 7.3.4.2 Digital Interface
        3. 7.3.4.3 DCLKIN
        4. 7.3.4.4 Output Scrambler
        5. 7.3.4.5 Output Bit Mapper
          1. 7.3.4.5.1 2-Wire Mode
          2. 7.3.4.5.2 1-Wire Mode
          3. 7.3.4.5.3 1/2-Wire Mode
        6. 7.3.4.6 Output Data Format
        7. 7.3.4.7 Test Pattern
      5. 7.3.5 Digital Down Converter
        1. 7.3.5.1 Decimation Operation
        2. 7.3.5.2 Numerically Controlled Oscillator (NCO)
        3. 7.3.5.3 Decimation Filters
        4. 7.3.5.4 SYNC
        5. 7.3.5.5 Output Data Format with Decimation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Low Latency Mode
      2. 7.4.2 Averaging Mode
    5. 7.5 Programming
      1. 7.5.1 Pin Control
      2. 7.5.2 Serial Peripheral Interface (SPI)
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
      3. 7.5.3 Device Configuration Steps
      4. 7.5.4 Register Map
        1. 7.5.4.1 Detailed Register Description
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
    3. 8.3 Initialization Set Up
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • HBP|64
サーマルパッド・メカニカル・データ
発注情報

7.3.4.4 Output Scrambler

The ADC3664-SP includes an optional output scrambler feature in 2-wire mode only. The scrambler can enabled by enabling the DSP features (D2 of 0x24) and enabling scrambling (D6 of 0x22). When enabled, each sample is split into two halves. Each half of the samples stream is scrambled independently. For example, if the samples stream is at an 18-bit resolution, the stream is divided into two halves consisting of bits D17-D9 & D8-D0. The two halves are fed into independent scrambling blocks where each input bit (x[k]) of each scrambler is XOR-ed with 2 previous bits (y[k-14] and y[k-15]) as shown in Figure 7-10. Since this is a self-synchronizing scrambler, the start up state of the scrambler can be ignored.

ADC3664-SP Scrambler and Descrambler OperationFigure 7-10 Scrambler and Descrambler Operation
Note: The sample streams fed into each scrambler are fed to the scrambler LSB first. Therefore, in the previous example, the sample stream half consisting of D8-D0 is provided to the scrambler with D0 first as x[k] followed by D1 as x[k+1] and so on.

For proper descrambling, the sample stream halves must be descrambled independently then the descrambled data can be used to reconstruct the samples. On the receiver side, the incoming serial data stream can be descrambled by XOR-ing each incoming bit (y[k]) with 2 previous bits (y[k-14] and y[k-15]).

Note: Since the scramblers are looking at the two halves of the sample stream, the output bit mapper needs to be configured such that each lane contains only one of the sample halves.

For example, in 2-wire and 18-bit mode, one lane carries the odd bits (D17, D15, D13, etc.) and one lane carries the even bits (D16, D14, D12, etc.). When scrambling is enabled, the bit mapper needs to be configured so that one lane carries bits D9-D17 and the other lane carries D0-D8 (LSB first for each lane). An example data flow diagram of scrambling an 18-bit sample stream is shown in Figure 7-11, where D17:D0 is the sample provided by the ADC after the resolution select block, the sample is split into D0-D8 and D9-D17 and fed into each scrambler (LSB first) and S0-S17 are the resultant scrambled bits.

ADC3664-SP 18-bit Scrambling ExampleFigure 7-11 18-bit Scrambling Example