JAJSKU4B December   2020  – July 2022 ADC3664

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - Power Consumption
    6. 6.6 Electrical Characteristics - DC Specifications
    7. 6.7 Electrical Characteristics - AC Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Output Formatter
        2. 8.3.5.2 Output Bit Mapper
        3. 8.3.5.3 Output Interface/Mode Configuration
          1. 8.3.5.3.1 Configuration Example
        4. 8.3.5.4 Output Data Format
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal operation
      2. 8.4.2 Power Down Options
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Maps
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.4.5 Decimation Filter

The ADC3664 supports complex decimation by 2, 4, 8, 16 and 32 with a pass-band bandwidth of ~ 80% and a stopband rejection of at least 85 dB. Table 8-2 gives an overview of the pass-band bandwidth of the different decimation settings with respect to ADC sampling rate FS. In real decimation mode the output bandwidth is half of the complex bandwidth.

Table 8-2 Decimation Filter Summary and Maximum Available Output Bandwidth
REAL/COMPLEX DECIMATIONDECIMATION SETTING NOUTPUT RATEOUTPUT BANDWIDTHOUTPUT RATE
(FS = 125 MSPS)		OUTPUT BANDWIDTH
(FS = 125 MSPS)
Complex2FS / 2 complex0.8 × FS / 262.5 MSPS complex50 MHz
4FS / 4 complex0.8 × FS / 431.25 MSPS complex25 MHz
8FS / 8 complex0.8 × FS / 815.625 MSPS complex12.5 MHz
16FS / 16 complex0.8 × FS / 167.8125 MSPS complex6.25 MHz
32FS / 32 complex0.8 × FS / 323.90625 MSPS complex3.125 MHz
Real2FS / 2 real0.4 × FS / 262.5 MSPS25 MHz
4FS / 4 real0.4 × FS / 431.25 MSPS12.5 MHz
8FS / 8 real0.4 × FS / 815.625 MSPS6.25 MHz
16FS / 16 real0.4 × FS / 167.8125 MSPS3.125 MHz
32FS / 32 real0.4 × FS / 323.90625 MSPS1.5625 MHz

The decimation filter responses normalized tot he ADC sampling clock frequency are illustrated in Figure 8-21 to Figure 8-30. They are interpreted as follows:

Each figure contains the filter pass-band, transition band(s) and alias or stop-band(s) as shown in Figure 8-20. The x-axis shows the offset frequency (after the NCO frequency shift) normalized to the ADC sampling rate FS.

For example, in the divide-by-4 complex setup, the output data rate is FS / 4 complex with a Nyquist zone of FS / 8 or 0.125 × FS. The transition band (colored in blue) is centered around 0.125 × FS and the alias transition band is centered at 0.375 × FS. The stop-bands (colored in red), which alias on top of the pass-band, are centered at 0.25 × FS and 0.5 × FS. The stop-band attenuation is greater than 85 dB.

GUID-57D38B26-F222-460E-9007-EB086B2A3C57-low.gifFigure 8-20 Interpretation of the Decimation Filter Plots
GUID-5CDEC19F-C7F5-4CBA-8BFE-8BAE9D7A0809-low.gifFigure 8-21 Decimation by 2 complex frequency response
GUID-371EBBC6-917C-4F6F-8C33-063D58F2D35D-low.gifFigure 8-23 Decimation by 4 complex frequency response
GUID-CC865698-152F-4461-91EF-4EC38EF5F87A-low.gifFigure 8-25 Decimation by 8 complex frequency response
GUID-C9C253FA-52EC-469C-9674-39888C3E6300-low.gifFigure 8-27 Decimation by 16 complex frequency response
GUID-4F40C789-29CD-4A11-9B89-685B3BCA5A2C-low.gifFigure 8-29 Decimation by 32 complex frequency response
GUID-F0952B89-861F-4D74-974F-28381FB46FF6-low.gifFigure 8-22 Decimation by 2 complex passband ripple response
GUID-E8CF6FEF-E52A-49BC-8548-6A60E88A8BE7-low.gifFigure 8-24 Decimation by 4 complex passband ripple response
GUID-34A10535-3973-4D67-BDE2-63ED3F46079C-low.gifFigure 8-26 Decimation by 8 complex passband ripple response
GUID-958CCB81-800E-4799-8B07-7AE026F0C254-low.gifFigure 8-28 Decimation by 16 complex passband ripple response
GUID-77B5B94D-FA91-482C-B234-15BA45742D6E-low.gifFigure 8-30 Decimation by 32 complex passband ripple response