JAJSLC0 March   2024 ADC3683-SP

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Front End Design
          1. 7.3.1.1.1 Sampling Glitch Filter Design
          2. 7.3.1.1.2 Analog Input Termination and DC Bias
            1. 7.3.1.1.2.1 AC-Coupling
            2. 7.3.1.1.2.2 DC-Coupling
        2. 7.3.1.2 Auto-Zero Feature
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Single Ended vs Differential Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference (VREF)
        3. 7.3.3.3 External Voltage Reference with Internal Buffer (REFBUF)
      4. 7.3.4 Digital Down Converter
        1. 7.3.4.1 DDC MUX
        2. 7.3.4.2 Digital Filter Operation
        3. 7.3.4.3 FS/4 Mixing with Real Output
        4. 7.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 7.3.4.5 Decimation Filter
        6. 7.3.4.6 SYNC
        7. 7.3.4.7 Output Formatting with Decimation
      5. 7.3.5 Digital Interface
        1. 7.3.5.1 Output Formatter
        2. 7.3.5.2 Output Scrambler
        3. 7.3.5.3 Output Bit Mapper
          1. 7.3.5.3.1 2-Wire Mode
          2. 7.3.5.3.2 1-Wire Mode
          3. 7.3.5.3.3 ½-Wire Mode
        4. 7.3.5.4 Output Interface or Mode Configuration
          1. 7.3.5.4.1 Configuration Example
        5. 7.3.5.5 Output Data Format
      6. 7.3.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down Options
      3. 7.4.3 Digital Channel Averaging
    5. 7.5 Programming
      1. 7.5.1 Configuration using PINs only
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Sampling Clock
        3. 8.2.2.3 Voltage Reference
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Register Initialization During Operation
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Map
    1. 9.1 Detailed Register Description
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.5.3 Output Bit Mapper

The output bit mapper allows change to the output bit order for any selected interface mode.

GUID-2DA0AF52-4C30-4465-8354-F73FFC67D3CD-low.svgFigure 7-39 Output Bit Mapper

There is a two step process to change the output bit mapping and assemble the output data bus:

  1. Both channel A and B can have up to 20-bit output. Each output bit of either channel has a unique identifier bit as shown in Table 7-7. The MSB starts with bit D19, depending on output resolution chosen, the LSB is D6 (14-bit) to D0 (20-bit). The previous sample is only needed in 2-w mode.
  2. The bit mapper is then used to assemble the output sample. The following sections detail how to remap the serial output format.

Table 7-7 Unique identifier of each data bit
BitChannel AChannel B
Previous sample (2w only)Current samplePrevious sample (2w only)Current sample
D19 (MSB)0x2D0x6D0x290x69
D180x2C0x6C0x280x68
D170x270x670x230x63
D160x260x660x220x62
D150x250x650x210x61
D140x240x640x200x60
D130x1F0x5F0x1B0x5B
D120x1E0x5E0x1A0x5A
D110x1D0x5D0x190x59
D100x1C0x5C0x180x58
D90x170x570x130x53
D80x160x560x120x52
D70x150x550x110x51
D60x140x540x100x50
D50x0F0x4F0x0B0x4B
D40x0E0x4E0x0A0x4A
D30x0D0x4D0x090x49
D20x0C0x4C0x080x48
D10x070x470x030x43
D0 (LSB)0x060x460x020x42

In the serial output mode, a data bit (with unique identifier) needs to be assigned to each location within the serial output stream. There are a total of 40 addresses available per channel. Channel A spans from address 0x39 to 0x60 and channel B from address 0x61 to 0x88. When using complex decimation, the output bit mapper is applied to both the “I” and the “Q” sample.