JAJSLC0 March   2024 ADC3683-SP

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Front End Design
          1. 7.3.1.1.1 Sampling Glitch Filter Design
          2. 7.3.1.1.2 Analog Input Termination and DC Bias
            1. 7.3.1.1.2.1 AC-Coupling
            2. 7.3.1.1.2.2 DC-Coupling
        2. 7.3.1.2 Auto-Zero Feature
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Single Ended vs Differential Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference (VREF)
        3. 7.3.3.3 External Voltage Reference with Internal Buffer (REFBUF)
      4. 7.3.4 Digital Down Converter
        1. 7.3.4.1 DDC MUX
        2. 7.3.4.2 Digital Filter Operation
        3. 7.3.4.3 FS/4 Mixing with Real Output
        4. 7.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 7.3.4.5 Decimation Filter
        6. 7.3.4.6 SYNC
        7. 7.3.4.7 Output Formatting with Decimation
      5. 7.3.5 Digital Interface
        1. 7.3.5.1 Output Formatter
        2. 7.3.5.2 Output Scrambler
        3. 7.3.5.3 Output Bit Mapper
          1. 7.3.5.3.1 2-Wire Mode
          2. 7.3.5.3.2 1-Wire Mode
          3. 7.3.5.3.3 ½-Wire Mode
        4. 7.3.5.4 Output Interface or Mode Configuration
          1. 7.3.5.4.1 Configuration Example
        5. 7.3.5.5 Output Data Format
      6. 7.3.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down Options
      3. 7.4.3 Digital Channel Averaging
    5. 7.5 Programming
      1. 7.5.1 Configuration using PINs only
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Sampling Clock
        3. 8.2.2.3 Voltage Reference
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Register Initialization During Operation
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Map
    1. 9.1 Detailed Register Description
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

Figure 4-1 HBP Package, 64-Pin CFP
(Top View)
Table 4-1 Pin Functions
PINTYPEDESCRIPTION
NAMENO.
INPUT/REFERENCE
AINP21IPositive analog input, channel A
AINM22INegative analog input, channel A
BINP60IPositive analog input, channel B
BINM59INegative analog input, channel B
REFBUF6I1.2V external voltage reference input for use with internal reference buffer. Internal 100kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions.
REFGND5IReference ground input
VCM11OCommon-mode voltage output for the analog inputs, 0.95V
VREF4IExternal voltage reference input, 1.6V
CLOCK
CLKP8IPositive differential sampling clock input for the ADC
CLKM9INegative differential sampling clock input for the ADC
CONFIGURATION
NC1, 2, 10, 14, 15, 16, 17, 18, 19, 30, 31, 32, 33, 34, 41, 45, 46, 47, 48, 49, 50, 51, 62, 63, 64-Unbonded pins. Connect to ground or leave floating.(1)
PDN/SYNC3IPower down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21kΩ pull-down resistor.
RESET12IHardware reset. Active high. This pin has an internal 21kΩ pull-down resistor.
SEN25ISerial interface enable. Active low. This pin has an internal 21kΩ pull-up resistor to AVDD.
SCLK56ISerial interface clock input. This pin has an internal 21kΩ pull-down resistor.
SDIO13I/OSerial interface data input and output. This pin has an internal 21kΩ pull-down resistor.
DIGITAL INTERFACE
DA0P29OPositive differential serial LVDS output for lane 0, channel A
DA0M28ONegative differential serial LVDS output for lane 0, channel A
DA1P27OPositive differential serial LVDS output for lane 1, channel A
DA1M26ONegative differential serial LVDS output for lane 1, channel A
DB0P52OPositive differential serial LVDS output for lane 0, channel B
DB0M53ONegative differential serial LVDS output for lane 0, channel B
DB1P54OPositive differential serial LVDS output for lane 1, channel B
DB1M55ONegative differential serial LVDS output for lane 1, channel B
DCLKP37OPositive differential serial LVDS bit clock output.
DCLKM36ONegative differential serial LVDS bit clock output.
DCLKINP39IPositive differential serial LVDS bit clock input. Internal 100Ω differential termination.
DCLKINM38INegative differential serial LVDS bit clock input. Internal 100Ω differential termination.
FCLKP42OPositive differential serial LVDS frame clock output.
FCLKM43ONegative differential serial LVDS frame clock output.
POWER SUPPLY
AVDD7, 24, 57IAnalog 1.8V power supply
GND20, 23, 58, 61IGround, 0V
IOVDD35, 44I1.8V power supply for digital interface
IOGND40IGround, 0V for digital interface
DAPDAP-Die attached pad (thermal pad), connect to GND.
(1) Thermal pad and top metal lid are connected to pin 17. Can be grounded or no connect.