JAJSLC0 March   2024 ADC3683-SP

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Front End Design
          1. 7.3.1.1.1 Sampling Glitch Filter Design
          2. 7.3.1.1.2 Analog Input Termination and DC Bias
            1. 7.3.1.1.2.1 AC-Coupling
            2. 7.3.1.1.2.2 DC-Coupling
        2. 7.3.1.2 Auto-Zero Feature
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Single Ended vs Differential Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference (VREF)
        3. 7.3.3.3 External Voltage Reference with Internal Buffer (REFBUF)
      4. 7.3.4 Digital Down Converter
        1. 7.3.4.1 DDC MUX
        2. 7.3.4.2 Digital Filter Operation
        3. 7.3.4.3 FS/4 Mixing with Real Output
        4. 7.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 7.3.4.5 Decimation Filter
        6. 7.3.4.6 SYNC
        7. 7.3.4.7 Output Formatting with Decimation
      5. 7.3.5 Digital Interface
        1. 7.3.5.1 Output Formatter
        2. 7.3.5.2 Output Scrambler
        3. 7.3.5.3 Output Bit Mapper
          1. 7.3.5.3.1 2-Wire Mode
          2. 7.3.5.3.2 1-Wire Mode
          3. 7.3.5.3.3 ½-Wire Mode
        4. 7.3.5.4 Output Interface or Mode Configuration
          1. 7.3.5.4.1 Configuration Example
        5. 7.3.5.5 Output Data Format
      6. 7.3.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down Options
      3. 7.4.3 Digital Channel Averaging
    5. 7.5 Programming
      1. 7.5.1 Configuration using PINs only
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Sampling Clock
        3. 8.2.2.3 Voltage Reference
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Register Initialization During Operation
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Map
    1. 9.1 Detailed Register Description
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.5.1 Output Formatter

The digital output interface uses a flexible output bit mapper (Figure 7-36). The bit mapper takes the 18-bit output directly from the ADC or from the digital decimation filter block and reformats it to a resolution of 14,16,18 or 20-bit. The output serialization factor is adjusted accordingly for 2-, 1- and 1/2-wire interface modes. The maximum SLVDS interface output data rate can not be exceeded independent of output resolution or serialization factor.

For 14 and 16-bit output resolution, the LSBs are truncated during the reformatting. With 20-bit output, in bypass mode two 0s are added in place of the two LSBs while in decimation mode. The digital averaging mode with the full 20-bit output is used.

GUID-6453C8EC-E7B5-479F-9455-5CC2B8B09DD6-low.svgFigure 7-36 Interface Output Bit Mapper

Table 7-6 provides an overview for the resulting serialization factor depending on output resolution and output modes. Note that the DCLKIN frequency needs to be adjusted accordingly as well. Changing the output resolution to 16-bit, 2-wire mode for example results in DCLKIN = FS * 4 instead of * 4.5.

The programming sequence for changing the output interface and/or resolution from default settings is shown in Section 7.3.5.4.

Table 7-6 Serialization Factor vs Output Resolution for Different Output Modes
OUTPUT RESOLUTIONInterfaceSERIALIZATIONFCLKDCLKINDCLKD0/D1
14-bit2-Wire7xFS/2FS* 3.5FS* 3.5FS* 7
1-Wire14xFSFS* 7FS* 7FS* 14
1/2-Wire28xFSFS* 14FS* 14FS* 28
16-bit2-Wire8xFS/2FS* 4FS* 4FS* 8
1-Wire16xFSFS* 8FS* 8FS* 16
1/2-Wire32xFSFS* 16FS* 16FS* 32
18-bit (default)2-Wire9xFS/2FS* 4.5FS* 4.5FS* 9
1-Wire18xFSFS* 9FS* 9FS* 18
1/2-Wire36xFSFS* 18FS* 18FS* 36
20-bit2-Wire10xFS/2FS* 5FS* 5FS* 10
1-Wire20xFSFS* 10FS* 10FS* 20
1/2-Wire40xFSFS* 20FS* 20FS* 40