JAJSLC0 March   2024 ADC3683-SP

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Front End Design
          1. 7.3.1.1.1 Sampling Glitch Filter Design
          2. 7.3.1.1.2 Analog Input Termination and DC Bias
            1. 7.3.1.1.2.1 AC-Coupling
            2. 7.3.1.1.2.2 DC-Coupling
        2. 7.3.1.2 Auto-Zero Feature
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Single Ended vs Differential Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference (VREF)
        3. 7.3.3.3 External Voltage Reference with Internal Buffer (REFBUF)
      4. 7.3.4 Digital Down Converter
        1. 7.3.4.1 DDC MUX
        2. 7.3.4.2 Digital Filter Operation
        3. 7.3.4.3 FS/4 Mixing with Real Output
        4. 7.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 7.3.4.5 Decimation Filter
        6. 7.3.4.6 SYNC
        7. 7.3.4.7 Output Formatting with Decimation
      5. 7.3.5 Digital Interface
        1. 7.3.5.1 Output Formatter
        2. 7.3.5.2 Output Scrambler
        3. 7.3.5.3 Output Bit Mapper
          1. 7.3.5.3.1 2-Wire Mode
          2. 7.3.5.3.2 1-Wire Mode
          3. 7.3.5.3.3 ½-Wire Mode
        4. 7.3.5.4 Output Interface or Mode Configuration
          1. 7.3.5.4.1 Configuration Example
        5. 7.3.5.5 Output Data Format
      6. 7.3.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down Options
      3. 7.4.3 Digital Channel Averaging
    5. 7.5 Programming
      1. 7.5.1 Configuration using PINs only
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Sampling Clock
        3. 8.2.2.3 Voltage Reference
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Register Initialization During Operation
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Map
    1. 9.1 Detailed Register Description
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 Electrical Characteristics - DC Specifications

Typical values are at TA = 25°C, full temperature range is TMIN = –55°C to TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
No missing codes 18 bits
PSRR FIN = 1 MHz 50 dB
ADC3683-SP: 65 MSPS
DNL Differential nonlinearity FIN = 5 MHz -0.9 ± 0.7 1.7 LSB
INL Integral nonlinearity FIN = 5 MHz ± 7 ± 21.5 LSB
VOS_ERR Offset error ± 130 ± 510 LSB
VOS_DRIFT Offset drift over temperature ± 0.2 LSB/ºC
GAINERR Gain error External 1.6V Reference ± 1.7 %FSR
GAINDRIFT Gain drift over temperature External 1.6V Reference 68 ppm/ºC
GAINERR Gain error Internal Reference -5 1.3 +5 %FSR
Internal Reference, Fs= 10 MSPS -2.5 0.2 +2.5 %FSR
GAINDRIFT Gain drift over temperature Internal Reference 242 ppm/ºC
Transition Noise 5 LSB
ADC ANALOG INPUT (AINP/M, BINP/M)
FS Input full scale Differential  3.2 Vpp
VCM Input common model voltage 0.95 V
RIN Differential input resistance FIN = 100 kHz 8 kΩ
CIN Differential input Capacitance FIN = 100 kHz 7 pF
VOCM Output common mode voltage 0.95 V
BW Analog Input Bandwidth (-3dB) 140 MHz
Internal Voltage Reference
VREF Internal reference voltage 1.6 V
VREF Output Impedance 8 Ω
Reference Input Buffer (REFBUF)
External reference voltage 1.2 V
External voltage reference (VREF)
VREF External voltage reference 1.6 V
Input Current 0.3 mA
Input impedance 5.3 kΩ
Clock Input (CLKP/M)
Input clock frequency 1 65 MHz
VID Differential input voltage 1 Vpp
VCM Input common mode voltage 0.9 V
RIN Single ended input resistance to common mode 5 kΩ
CIN Single ended input capacitance 1.5 pF
Clock duty cycle 40 50 60 %
Digital Inputs (RESET, PDN, SCLK, SEN, SDIO)
VIH High level input voltage 1.5 V
VIL Low level input voltage 0.3 V
IIH High level input current 90 150 uA
IIL Low level input current -150 -90 uA
CI Input capacitance 1.5 pF
Digital Output (SDOUT)
VOH High level output voltage ILOAD = -400 uA IOVDD – 0.1 IOVDD V
VOL Low level output voltage ILOAD = 400 uA 0.1 V
SLVDS Interface
Output data rate per differential SLVDS output pair 1000 Mbps
VID Differential input voltage DCLKIN (1) 350 mVpp
VCM Input common mode voltage 1.2 V
VOD Differential output voltage 700 mVpp
VCM Output common mode voltage 1.0 V
(1) Vcm needs to be provided externally by default. Otherwise, see reg map.