JAJSA35G April   2003  – May 2016 ADCS7476 , ADCS7477 , ADCS7478

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - ADCS7476
    6. 6.6 Electrical Characteristics - ADCS7477
    7. 6.7 Electrical Characteristics - ADCS7478
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Transfer Function
      2. 7.4.2 Power-Up Timing
      3. 7.4.3 Modes of Operation
        1. 7.4.3.1 Normal Mode
        2. 7.4.3.2 Start-Up Mode
        3. 7.4.3.3 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Analog Inputs
      2. 8.1.2 Digital Inputs and Outputs
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Noise
    2. 9.2 Digital Output Effect Upon Noise
    3. 9.3 Power Management
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デバイスの関連用語
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

DBV Package
6-Pin SOT-23
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NO. NAME
1 VDD P Positive supply pin. These pins must be connected to a quiet 2.7-V to 5.25-V source and bypassed to GND with 0.1-µF and 1-µF monolithic capacitors placed within 1 cm of the power pin. ADCS747x uses this power supply as a reference, so it must be thoroughly bypassed.
2 GND G The ground return for the supply.
3 VIN I Analog input. This signal can range from 0 V to VDD.
4 SCLK I Digital clock input. The range of frequencies for this input is 10 kHz to 20 MHz, with ensured performance at 20 MHz. This clock directly controls the conversion and readout processes.
5 SDATA O Digital data output. The output words are clocked out of this pin by the SCLK pin.
6 CS I Chip select. A conversion process begins on the falling edge of CS.
(1) G = Ground, I = Input, O = Output, P = Power