JAJSEC6E july   2010  – july 2023 ADS1013-Q1 , ADS1014-Q1 , ADS1015-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6.   Device Comparison Table
  7. 5 Pin Configuration and Functions
  8. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: I2C
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Multiplexer
      2. 7.3.2 Analog Inputs
      3. 7.3.3 Full-Scale Range (FSR) and LSB Size
      4. 7.3.4 Voltage Reference
      5. 7.3.5 Oscillator
      6. 7.3.6 Output Data Rate and Conversion Time
      7. 7.3.7 Digital Comparator (ADS1014-Q1 and ADS1015-Q1 Only)
      8. 7.3.8 Conversion Ready Pin (ADS1014-Q1 and ADS1015-Q1 Only)
      9. 7.3.9 SMbus Alert Response
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset and Power-Up
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Single-Shot Mode
        2. 7.4.2.2 Continuous-Conversion Mode
      3. 7.4.3 Duty Cycling For Low Power
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 I2C Address Selection
        2. 7.5.1.2 I2C General Call
        3. 7.5.1.3 I2C Speed Modes
      2. 7.5.2 Target Mode Operations
        1. 7.5.2.1 Receive Mode
        2. 7.5.2.2 Transmit Mode
      3. 7.5.3 Writing To and Reading From the Registers
      4. 7.5.4 Data Format
    6. 7.6 Register Map
      1. 7.6.1 Address Pointer Register (address = N/A) [reset = N/A]
      2. 7.6.2 Conversion Register (P[1:0] = 00b) [reset = 0000h]
      3. 7.6.3 Config Register (P[1:0] = 01b) [reset = 8583h]
      4. 7.6.4 Lo_thresh (P[1:0] = 10b) [reset = 8000h] and Hi_thresh (P[1:0] = 11b) [reset = 7FFFh] Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Connections
      2. 8.1.2 Single-Ended Inputs
      3. 8.1.3 Input Protection
      4. 8.1.4 Unused Inputs and Outputs
      5. 8.1.5 Analog Input Filtering
      6. 8.1.6 Connecting Multiple Devices
      7. 8.1.7 Quick-Start Guide
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Shunt Resistor Considerations
        2. 8.2.2.2 Operational Amplifier Considerations
        3. 8.2.2.3 ADC Input Common-Mode Considerations
        4. 8.2.2.4 Resistor (R1, R2, R3, R4) Considerations
        5. 8.2.2.5 Noise and Input Impedance Considerations
        6. 8.2.2.6 First-Order RC Filter Considerations
        7. 8.2.2.7 Circuit Implementation
        8. 8.2.2.8 Results Summary
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Supply Sequencing
      2. 8.3.2 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  12. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.2 Analog Inputs

The ADS101x-Q1 use a switched-capacitor input stage where capacitors are continuously charged and then discharged to measure the voltage between AINP and AINN. The frequency at which the input signal is sampled is called the sampling frequency or the modulator frequency (fMOD). The ADS101x-Q1 has a 1-MHz internal oscillator that is further divided by a factor of 4 to generate fMOD at 250 kHz. The capacitors used in this input stage are small, and to external circuitry, the average loading appears resistive. Figure 7-5 shows this structure. The capacitor values set the resistance and switching rate. Figure 7-6 shows the timing for the switches in Figure 7-5. During the sampling phase, switches S1 are closed. This event charges CA1 to V(AINP), CA2 to V(AINN), and CB to (V(AINP) – V(AINN)). During the discharge phase, S1 is first opened and then S2 is closed. Both CA1 and CA2 then discharge to approximately 0.7 V and CB discharges to 0 V. This charging draws a very small transient current from the source driving the ADS101x-Q1 analog inputs. The average value of this current can be used to calculate the effective impedance (Zeff), where Zeff = VIN / IAVERAGE.

GUID-F44230CC-193F-41CC-A864-84399DBB247E-low.gifFigure 7-5 Simplified Analog Input Circuit
GUID-7BE6C58E-4AE0-4823-96B3-19D2BF4342A9-low.gifFigure 7-6 S1 and S2 Switch Timing

The common-mode input impedance is measured by applying a common-mode signal to the shorted AINP and AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance changes depending on the full-scale range, but is approximately 6 MΩ for the default full-scale range. In Figure 7-5, the common-mode input impedance is ZCM.

The differential input impedance is measured by applying a differential signal to AINP and AINN inputs where one input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and scales with the full-scale range. In Figure 7-5, the differential input impedance is ZDIFF.

Make sure to consider the typical value of the input impedance. Unless the input source has a low impedance, the ADS101x-Q1 input impedance can affect the measurement accuracy. For sources with high-output impedance, buffering may be necessary. Active buffers introduce noise, and also introduce offset and gain errors. Consider all of these factors in high-accuracy applications.

The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most applications, this input impedance drift is negligible, and can be ignored.