JAJSEC7E May   2009  – January 2018 ADS1013 , ADS1014 , ADS1015

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略ブロック図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: I2C
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer
      2. 8.3.2 Analog Inputs
      3. 8.3.3 Full-Scale Range (FSR) and LSB Size
      4. 8.3.4 Voltage Reference
      5. 8.3.5 Oscillator
      6. 8.3.6 Output Data Rate and Conversion Time
      7. 8.3.7 Digital Comparator (ADS1014 and ADS1015 Only)
      8. 8.3.8 Conversion Ready Pin (ADS1014 and ADS1015 Only)
      9. 8.3.9 SMbus Alert Response
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset and Power-Up
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Single-Shot Mode
        2. 8.4.2.2 Continuous-Conversion Mode
      3. 8.4.3 Duty Cycling For Low Power
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 I2C Address Selection
        2. 8.5.1.2 I2C General Call
        3. 8.5.1.3 I2C Speed Modes
      2. 8.5.2 Slave Mode Operations
        1. 8.5.2.1 Receive Mode
        2. 8.5.2.2 Transmit Mode
      3. 8.5.3 Writing To and Reading From the Registers
      4. 8.5.4 Data Format
    6. 8.6 Register Map
      1. 8.6.1 Address Pointer Register (address = N/A) [reset = N/A]
        1. Table 4. Address Pointer Register Field Descriptions
      2. 8.6.2 Conversion Register (P[1:0] = 0h) [reset = 0000h]
        1. Table 5. Conversion Register Field Descriptions
      3. 8.6.3 Config Register (P[1:0] = 1h) [reset = 8583h]
        1. Table 6. Config Register Field Descriptions
      4. 8.6.4 Lo_thresh (P[1:0] = 2h) [reset = 8000h] and Hi_thresh (P[1:0] = 3h) [reset = 7FFFh] Registers
        1. Table 7. Lo_thresh and Hi_thresh Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Basic Connections
      2. 9.1.2 Single-Ended Inputs
      3. 9.1.3 Input Protection
      4. 9.1.4 Unused Inputs and Outputs
      5. 9.1.5 Analog Input Filtering
      6. 9.1.6 Connecting Multiple Devices
      7. 9.1.7 Quickstart Guide
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Shunt Resistor Considerations
        2. 9.2.2.2 Operational Amplifier Considerations
        3. 9.2.2.3 ADC Input Common-Mode Considerations
        4. 9.2.2.4 Resistor (R1, R2, R3, R4) Considerations
        5. 9.2.2.5 Noise and Input Impedance Considerations
        6. 9.2.2.6 First-order RC Filter Considerations
        7. 9.2.2.7 Circuit Implementation
        8. 9.2.2.8 Results Summary
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
    2. 10.2 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6.3 Config Register (P[1:0] = 1h) [reset = 8583h]

The 16-bit Config register is used to control the operating mode, input selection, data rate, full-scale range, and comparator modes.

Figure 21. Config Register
15 14 13 12 11 10 9 8
OS MUX[2:0] PGA[2:0] MODE
R/W-1h R/W-0h R/W-2h R/W-1h
7 6 5 4 3 2 1 0
DR[2:0] COMP_MODE COMP_POL COMP_LAT COMP_QUE[1:0]
R/W-4h R/W-0h R/W-0h R/W-0h R/W-3h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. Config Register Field Descriptions

BitFieldTypeResetDescription
15 OS R/W 1h Operational status or single-shot conversion start
This bit determines the operational status of the device. OS can only be written when in power-down state and has no effect when a conversion is ongoing.



When writing:
0 : No effect
1 : Start a single conversion (when in power-down state)

When reading:
0 : Device is currently performing a conversion
1 : Device is not currently performing a conversion
14:12 MUX[2:0] R/W 0h Input multiplexer configuration (ADS1015 only)
These bits configure the input multiplexer. These bits serve no function on the ADS1013 and ADS1014.



000 : AINP = AIN0 and AINN = AIN1 (default)
001 : AINP = AIN0 and AINN = AIN3
010 : AINP = AIN1 and AINN = AIN3
011 : AINP = AIN2 and AINN = AIN3
100 : AINP = AIN0 and AINN = GND
101 : AINP = AIN1 and AINN = GND
110 : AINP = AIN2 and AINN = GND
111 : AINP = AIN3 and AINN = GND
11:9 PGA[2:0] R/W 2h Programmable gain amplifier configuration
These bits set the FSR of the programmable gain amplifier. These bits serve no function on the ADS1013.


000 : FSR = ±6.144 V(1)
001 : FSR = ±4.096 V(1)
010 : FSR = ±2.048 V (default)
011 : FSR = ±1.024 V
100 : FSR = ±0.512 V
101 : FSR = ±0.256 V
110 : FSR = ±0.256 V
111 : FSR = ±0.256 V
8 MODE R/W 1h Device operating mode
This bit controls the operating mode.


0 : Continuous-conversion mode
1 : Single-shot mode or power-down state (default)
7:5 DR[2:0] R/W 4h Data rate
These bits control the data rate setting.


000 : 128 SPS
001 : 250 SPS
010 : 490 SPS
011 : 920 SPS
100 : 1600 SPS (default)
101 : 2400 SPS
110 : 3300 SPS
111 : 3300 SPS
4 COMP_MODE R/W 0h Comparator mode (ADS1014 and ADS1015 only)
This bit configures the comparator operating mode. This bit serves no function on the ADS1013.


0 : Traditional comparator (default)
1 : Window comparator
3 COMP_POL R/W 0h Comparator polarity (ADS1014 and ADS1015 only)
This bit controls the polarity of the ALERT/RDY pin. This bit serves no function on the ADS1013.


0 : Active low (default)
1 : Active high
2 COMP_LAT R/W 0h Latching comparator (ADS1014 and ADS1015 only)
This bit controls whether the ALERT/RDY pin latches after being asserted or clears after conversions are within the margin of the upper and lower threshold values. This bit serves no function on the ADS1013.


0 : Nonlatching comparator . The ALERT/RDY pin does not latch when asserted (default).
1 : Latching comparator. The asserted ALERT/RDY pin remains latched until conversion data are read by the master or an appropriate SMBus alert response is sent by the master. The device responds with its address, and it is the lowest address currently asserting the ALERT/RDY bus line.
1:0 COMP_QUE[1:0] R/W 3h Comparator queue and disable (ADS1014 and ADS1015 only)
These bits perform two functions. When set to 11, the comparator is disabled and the ALERT/RDY pin is set to a high-impedance state. When set to any other value, the ALERT/RDY pin and the comparator function are enabled, and the set value determines the number of successive conversions exceeding the upper or lower threshold required before asserting the ALERT/RDY pin. These bits serve no function on the ADS1013.


00 : Assert after one conversion

01 : Assert after two conversions

10 : Assert after four conversions

11 : Disable comparator and set ALERT/RDY pin to high-impedance (default)
(1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to the analog inputs of the device.