JAJSEC5E December   2011  – December 2022 ADS1113-Q1 , ADS1114-Q1 , ADS1115-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
    1.     Device Comparison Table
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: I2C
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer
      2. 8.3.2 Analog Inputs
      3. 8.3.3 Full-Scale Range (FSR) and LSB Size
      4. 8.3.4 Voltage Reference
      5. 8.3.5 Oscillator
      6. 8.3.6 Output Data Rate and Conversion Time
      7. 8.3.7 Digital Comparator (ADS1114-Q1 and ADS1115-Q1 Only)
      8. 8.3.8 Conversion Ready Pin (ADS1114-Q1 and ADS1115-Q1 Only)
      9. 8.3.9 SMBus のアラート応答
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset and Power-Up
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Single-Shot Mode
        2. 8.4.2.2 Continuous-Conversion Mode
      3. 8.4.3 Duty Cycling For Low Power
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 I2C Address Selection
        2. 8.5.1.2 I2C General Call
        3. 8.5.1.3 I2C Speed Modes
      2. 8.5.2 Target Mode Operations
        1. 8.5.2.1 Receive Mode
        2. 8.5.2.2 Transmit Mode
      3. 8.5.3 Writing To and Reading From the Registers
      4. 8.5.4 Data Format
    6. 8.6 Register Map
      1. 8.6.1 Address Pointer Register (address = N/A) [reset = N/A]
      2. 8.6.2 Conversion Register (P[1:0] = 00b) [reset = 0000h]
      3. 8.6.3 Config Register (P[1:0] = 01b) [reset = 8583h]
      4. 8.6.4 Lo_thresh (P[1:0] = 10b) [reset = 8000h] and Hi_thresh (P[1:0] = 11b) [reset = 7FFFh] Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Basic Connections
      2. 9.1.2 Single-Ended Inputs
      3. 9.1.3 Input Protection
      4. 9.1.4 Unused Inputs and Outputs
      5. 9.1.5 Analog Input Filtering
      6. 9.1.6 Connecting Multiple Devices
      7. 9.1.7 Quick-Start Guide
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Shunt Resistor Considerations
        2. 9.2.2.2 Operational Amplifier Considerations
        3. 9.2.2.3 ADC Input Common-Mode Considerations
        4. 9.2.2.4 Resistor (R1, R2, R3, R4) Considerations
        5. 9.2.2.5 Noise and Input Impedance Considerations
        6. 9.2.2.6 First-Order RC Filter Considerations
        7. 9.2.2.7 Circuit Implementation
        8. 9.2.2.8 Results Summary
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Sequencing
      2. 9.3.2 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.1.7 Quick-Start Guide

This section provides a brief example of ADS111x-Q1 communications. Hardware for this design includes: one ADS111x-Q1 configured with an I2C address of 1001000b; a microcontroller with an I2C interface; discrete components such as resistors, capacitors, and serial connectors; and a 2-V to 5-V power supply. Figure 9-5 shows the basic hardware configuration.

The ADS111x-Q1 communicate with the controller (microcontroller) through an I2C interface. The controller provides a clock signal on the SCL pin and data are transferred using the SDA pin. The ADS111x-Q1 never drive the SCL pin. For information on programming and debugging the microcontroller being used, see the device-specific product data sheet.

The first byte sent by the controller is the ADS111x-Q1 address, followed by the R/W bit that instructs the ADS111x-Q1 to listen for a subsequent byte. The second byte is the Address Pointer register byte. The third and fourth bytes sent from the controller are written to the register indicated in register address pointer bits P[1:0]. See Figure 8-9 and Figure 8-10 for read and write operation timing diagrams, respectively. All read and write transactions with the ADS111x-Q1 must be preceded by a START condition, and followed by a STOP condition.

For example, to write to the configuration register to set the ADS111x-Q1 to continuous-conversion mode and then read the conversion result, send the following bytes in this order:

  1. Write to Config register:
    • First byte: 10010000b (first 7-bit I2C address followed by a low R/W bit)
    • Second byte: 00000001b (points to Config register)
    • Third byte: 10000100b (MSB of the Config register to be written)
    • Fourth byte: 10000011b (LSB of the Config register to be written)
  2. Write to Address Pointer register:
    • First byte: 10010000b (first 7-bit I2C address followed by a low R/W bit)
    • Second byte: 00000000b (points to Conversion register)
  3. Read Conversion register:
    • First byte: 10010001b (first 7-bit I2C address followed by a high R/W bit)
    • Second byte: the ADS111x-Q1 response with the MSB of the Conversion register
    • Third byte: the ADS111x-Q1 response with the LSB of the Conversion register
Figure 9-5 Basic Hardware Configuration