JAJSEC5E December   2011  – December 2022 ADS1113-Q1 , ADS1114-Q1 , ADS1115-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
    1.     Device Comparison Table
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: I2C
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer
      2. 8.3.2 Analog Inputs
      3. 8.3.3 Full-Scale Range (FSR) and LSB Size
      4. 8.3.4 Voltage Reference
      5. 8.3.5 Oscillator
      6. 8.3.6 Output Data Rate and Conversion Time
      7. 8.3.7 Digital Comparator (ADS1114-Q1 and ADS1115-Q1 Only)
      8. 8.3.8 Conversion Ready Pin (ADS1114-Q1 and ADS1115-Q1 Only)
      9. 8.3.9 SMBus のアラート応答
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset and Power-Up
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Single-Shot Mode
        2. 8.4.2.2 Continuous-Conversion Mode
      3. 8.4.3 Duty Cycling For Low Power
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 I2C Address Selection
        2. 8.5.1.2 I2C General Call
        3. 8.5.1.3 I2C Speed Modes
      2. 8.5.2 Target Mode Operations
        1. 8.5.2.1 Receive Mode
        2. 8.5.2.2 Transmit Mode
      3. 8.5.3 Writing To and Reading From the Registers
      4. 8.5.4 Data Format
    6. 8.6 Register Map
      1. 8.6.1 Address Pointer Register (address = N/A) [reset = N/A]
      2. 8.6.2 Conversion Register (P[1:0] = 00b) [reset = 0000h]
      3. 8.6.3 Config Register (P[1:0] = 01b) [reset = 8583h]
      4. 8.6.4 Lo_thresh (P[1:0] = 10b) [reset = 8000h] and Hi_thresh (P[1:0] = 11b) [reset = 7FFFh] Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Basic Connections
      2. 9.1.2 Single-Ended Inputs
      3. 9.1.3 Input Protection
      4. 9.1.4 Unused Inputs and Outputs
      5. 9.1.5 Analog Input Filtering
      6. 9.1.6 Connecting Multiple Devices
      7. 9.1.7 Quick-Start Guide
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Shunt Resistor Considerations
        2. 9.2.2.2 Operational Amplifier Considerations
        3. 9.2.2.3 ADC Input Common-Mode Considerations
        4. 9.2.2.4 Resistor (R1, R2, R3, R4) Considerations
        5. 9.2.2.5 Noise and Input Impedance Considerations
        6. 9.2.2.6 First-Order RC Filter Considerations
        7. 9.2.2.7 Circuit Implementation
        8. 9.2.2.8 Results Summary
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Sequencing
      2. 9.3.2 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

at VDD = 3.3 V, data rate = 8 SPS, and full-scale input voltage range (FSR) = ±2.048 V (unless otherwise noted); maximum and minimum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ANALOG INPUT
Common-mode input impedanceFSR = ±6.144 V(1)10MΩ
FSR = ±4.096 V(1), FSR = ±2.048 V6
FSR = ±1.024 V3
FSR = ±0.512 V, FSR = ±0.256 V 100 kΩ
Differential input impedanceFSR = ±6.144 V(1)22MΩ
FSR = ±4.096 V(1)15
FSR = ±2.048 V4.9
FSR = ±1.024 V2.4
FSR = ±0.512 V, ±0.256 V710kΩ
SYSTEM PERFORMANCE
Resolution (no missing codes)16Bits
DRData rate8, 16, 32, 64, 128, 250, 475, 860SPS
Data rate variationAll data rates–10%10%
Output noiseSee Section 7.1 section
INLIntegral nonlinearityDR = 8 SPS, FSR = ±2.048 V(2)1LSB
Offset errorFSR = ±2.048 V, differential inputs–3±13LSB
FSR = ±2.048 V, single-ended inputs±3
Offset drift over temperatureFSR = ±2.048 V0.005LSB/°C
Long-term Offset driftFSR = ±2.048 V, TA = 125°C,
1000 hrs		±1LSB
Offset power-supply rejectionFSR = ±2.048 V, DC supply variation1LSB/V
Offset channel matchMatch between any two inputs3LSB
Gain error(3)FSR = ±2.048 V, TA = 25°C0.01%0.15%
Gain drift over temperature(3)FSR = ±0.256 V7ppm/°C
FSR = ±2.048 V540
FSR = ±6.144 V(1)5
Long-term gain drift(3)FSR = ±2.048 V, TA = 125°C,
1000 hrs		±0.05%
Gain power-supply rejection80ppm/V
Gain match(3)Match between any two gains0.02%0.1%
Gain channel matchMatch between any two inputs0.05%0.1%
CMRRCommon-mode rejection ratioAt DC, FSR = ±0.256 V105dB
At DC, FSR = ±2.048 V100
At DC, FSR = ±6.144 V(1)90
fCM = 60 Hz, DR = 8 SPS105
fCM = 50 Hz, DR = 8 SPS105
DIGITAL INPUT/OUTPUT
VIHHigh-level input voltage0.7 VDD5.5V
VILLow-level input voltageGND0.3 VDDV
VOLLow-level output voltageIOL = 3 mAGND0.150.4V
Input leakage currentGND < VDIG < VDD–1010µA
POWER-SUPPLY
IVDDSupply currentPower-downTA = 25°C0.52µA
5
OperatingTA = 25°C150200
300
PDPower dissipationVDD = 5.0 V0.9mW
VDD = 3.3 V0.5
VDD = 2.0 V0.3
(1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V must be applied to the analog inputs of the device. See Table 8-1 for more information.
(2) Best-fit INL; covers 99% of full-scale.
(3) Includes all errors from onboard PGA and voltage reference.