JAJSQJ6 December   2023 ADS1114L , ADS1115L

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer
      2. 8.3.2 Analog Inputs
      3. 8.3.3 Full-Scale Range (FSR) and LSB Size
      4. 8.3.4 Voltage Reference
      5. 8.3.5 Oscillator
      6. 8.3.6 Output Data Rate and Conversion Time
      7. 8.3.7 Digital Comparator
      8. 8.3.8 Conversion-Ready Pin
      9. 8.3.9 SMBus Alert Response
    4. 8.4 Device Functional Modes
      1. 8.4.1 Reset and Power-Up
      2. 8.4.2 Operating Modes
        1. 8.4.2.1 Single-Shot Mode
        2. 8.4.2.2 Continuous-Conversion Mode
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 I2C Address Selection
        2. 8.5.1.2 I2C Interface Speed
          1. 8.5.1.2.1 Serial Clock (SCL) and Serial Data (SDA)
        3. 8.5.1.3 I2C Data Transfer Protocol
        4. 8.5.1.4 Timeout
        5. 8.5.1.5 I2C General-Call (Software Reset)
      2. 8.5.2 Reading and Writing Register Data
        1. 8.5.2.1 Reading Conversion Data or the Configuration Register
        2. 8.5.2.2 Writing the Configuration Register
      3. 8.5.3 Data Format
  10. 9 Register Map
  11. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Basic Connections
      2. 10.1.2 Unused Inputs and Outputs
      3. 10.1.3 Single-Ended Inputs
      4. 10.1.4 Input Protection
      5. 10.1.5 Analog Input Filtering
      6. 10.1.6 Connecting Multiple Devices
      7. 10.1.7 Duty Cycling For Low Power
      8. 10.1.8 I2C Communication Sequence Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
    3. 10.3 Power Supply Recommendations
      1. 10.3.1 Power-Supply Sequencing
      2. 10.3.2 Power-Supply Decoupling
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5.1.3 I2C Data Transfer Protocol

Figure 8-8 shows the format of the data transfer. The controller initiates all transactions with the ADS111xL by generating a START (S) condition. A high-to-low transition on the SDA line while SCL is high defines a START condition. The bus is considered to be busy after the START condition.

Following the START condition, the controller sends the 7-bit target address corresponding to the address of the ADS111xL that the controller wants to communicate with. The controller then sends an eighth bit that is a data-direction bit (R/W). An R/W bit of 0b indicates a write operation, and an R/W bit of 1b indicates a read operation. After the R/W bit, the controller generates a ninth SCLK pulse and releases the SDA line to allow the ADS111xL to acknowledge (ACK) the reception of the target address by pulling SDA low. If the device does not recognize the target address, the ADS111xL holds SDA high to indicate a not acknowledge (NACK) signal.

Data transmission follows next in the process. If the transaction is a read (R/W = 1b), the ADS111xL outputs data on SDA. If the transaction is a write (R/W = 0b), the host outputs data on SDA. Data are transferred byte-wise, most significant bit (MSB) first. The number of bytes that can be transmitted per transfer is unrestricted. Each byte must be acknowledged (with the ACK bit) by the receiver. If the transaction is a read, the controller issues the ACK bit. If the transaction is a write, the ADS111xL issues the ACK bit.

The controller terminates all transactions by generating a STOP (P) condition. A low-to-high transition on the SDA line while SCL is high defines a STOP condition. The bus is considered free again tBUF (bus-free time) after the STOP condition.

GUID-20230711-SS0I-VWQL-3HHM-PW8XCQSSBK6L-low.svg Figure 8-8 I2C Data Transfer Format