JAJSDU5A August   2017  – February 2020 ADS114S06B , ADS114S08B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Multiplexer
      2. 9.3.2  Low-Noise Programmable Gain Amplifier
        1. 9.3.2.1 PGA Input-Voltage Requirements
        2. 9.3.2.2 Bypassing the PGA
      3. 9.3.3  Voltage Reference
        1. 9.3.3.1 Internal Reference
        2. 9.3.3.2 External Reference
        3. 9.3.3.3 Reference Buffers
      4. 9.3.4  Clock Source
      5. 9.3.5  Delta-Sigma Modulator
      6. 9.3.6  Digital Filter
        1. 9.3.6.1 Digital Filter Frequency Response
        2. 9.3.6.2 Data Conversion Time
        3. 9.3.6.3 Note on Conversion Time
        4. 9.3.6.4 50-Hz and 60-Hz Line Cycle Rejection
      7. 9.3.7  Excitation Current Sources (IDACs)
      8. 9.3.8  Bias Voltage Generation
      9. 9.3.9  System Monitor
        1. 9.3.9.1 Internal Temperature Sensor
        2. 9.3.9.2 Power Supply Monitors
        3. 9.3.9.3 Burn-Out Current Sources
      10. 9.3.10 Status Register
        1. 9.3.10.1 POR Flag
        2. 9.3.10.2 RDY Flag
        3. 9.3.10.3 External Reference Monitor
      11. 9.3.11 General-Purpose Inputs and Outputs (GPIOs)
      12. 9.3.12 Calibration
        1. 9.3.12.1 Offset Calibration
        2. 9.3.12.2 Gain Calibration
    4. 9.4 Device Functional Modes
      1. 9.4.1 Reset
        1. 9.4.1.1 Power-On Reset
        2. 9.4.1.2 RESET Pin
        3. 9.4.1.3 Reset by Command
      2. 9.4.2 Power-Down Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Conversion Modes
        1. 9.4.4.1 Continuous Conversion Mode
        2. 9.4.4.2 Single-Shot Conversion Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Serial Data Input (DIN)
        4. 9.5.1.4 Serial Data Output and Data Ready (DOUT/DRDY)
        5. 9.5.1.5 Data Ready (DRDY)
        6. 9.5.1.6 Timeout
      2. 9.5.2 Data Format
      3. 9.5.3 Commands
        1. 9.5.3.1  NOP
        2. 9.5.3.2  WAKEUP
        3. 9.5.3.3  POWERDOWN
        4. 9.5.3.4  RESET
        5. 9.5.3.5  START
        6. 9.5.3.6  STOP
        7. 9.5.3.7  SYOCAL
        8. 9.5.3.8  SYGCAL
        9. 9.5.3.9  SFOCAL
        10. 9.5.3.10 RDATA
        11. 9.5.3.11 RREG
        12. 9.5.3.12 WREG
      4. 9.5.4 Interfacing with Multiple Devices
    6. 9.6 Register Map
      1. 9.6.1 Configuration Registers
      2. 9.6.2 Register Descriptions
        1. 9.6.2.1  Device ID Register (address = 00h) [reset = xxh]
          1. Table 16. Device ID (ID) Register Field Descriptions
        2. 9.6.2.2  Device Status Register (address = 01h) [reset = 80h]
          1. Table 17. Device Status (STATUS) Register Field Descriptions
        3. 9.6.2.3  Input Multiplexer Register (address = 02h) [reset = 01h]
          1. Table 18. Input Multiplexer (INPMUX) Register Field Descriptions
        4. 9.6.2.4  Gain Setting Register (address = 03h) [reset = 00h]
          1. Table 19. Gain Setting (PGA) Register Field Descriptions
        5. 9.6.2.5  Data Rate Register (address = 04h) [reset = 14h]
          1. Table 20. Data Rate (DATARATE) Register Field Descriptions
        6. 9.6.2.6  Reference Control Register (address = 05h) [reset = 10h]
          1. Table 21. Reference Control (REF) Register Field Descriptions
        7. 9.6.2.7  Excitation Current Register 1 (address = 06h) [reset = 00h]
          1. Table 22. Excitation Current Register 1 (IDACMAG) Register Field Descriptions
        8. 9.6.2.8  Excitation Current Register 2 (address = 07h) [reset = FFh]
          1. Table 23. Excitation Current Register 2 (IDACMUX) Register Field Descriptions
        9. 9.6.2.9  Sensor Biasing Register (address = 08h) [reset = 00h]
          1. Table 24. Sensor Biasing (VBIAS) Register Field Descriptions
        10. 9.6.2.10 System Control Register (address = 09h) [reset = 10h]
          1. Table 25. System Control (SYS) Register Field Descriptions
        11. 9.6.2.11 Reserved Register (address = 0Ah) [reset = 00h]
          1. Table 26. Reserved Register Field Descriptions
        12. 9.6.2.12 Offset Calibration Register 1 (address = 0Bh) [reset = 00h]
          1. Table 27. Offset Calibration Register 1 (OFCAL0) Register Field Descriptions
        13. 9.6.2.13 Offset Calibration Register 2 (address = 0Ch) [reset = 00h]
          1. Table 28. Offset Calibration Register 2 (OFCAL1) Register Field Descriptions
        14. 9.6.2.14 Reserved Register (address = 0Dh) [reset = 00h]
          1. Table 29. Reserved Register Field Descriptions
        15. 9.6.2.15 Gain Calibration Register 1 (address = 0Eh) [reset = 00h]
          1. Table 30. Gain Calibration Register 1 (FSCAL0) Field Descriptions
        16. 9.6.2.16 Gain Calibration Register 2 (address = 0Fh) [reset = 40h]
          1. Table 31. Gain Calibration Register 2 (FSCAL1) Field Descriptions
        17. 9.6.2.17 GPIO Data Register (address = 10h) [reset = 00h]
          1. Table 32. GPIO Data (GPIODAT) Register Field Descriptions
        18. 9.6.2.18 GPIO Configuration Register (address = 11h) [reset = 00h]
          1. Table 33. GPIO Configuration (GPIOCON) Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Serial Interface Connections
      2. 10.1.2 Analog Input Filtering
      3. 10.1.3 External Reference and Ratiometric Measurements
      4. 10.1.4 Establishing a Proper Input Voltage
      5. 10.1.5 Unused Inputs and Outputs
      6. 10.1.6 Pseudo Code Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Register Settings
      3. 10.2.3 Application Curves
    3. 10.3 What To Do and What Not To Do
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
    2. 11.2 Power-Supply Sequencing
    3. 11.3 Power-On Reset
    4. 11.4 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHB|32
  • PBS|32
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal oscillator, and all data rates (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Absolute input current PGA bypassed,
AVSS + 0.1 V ≤ V(AINx) ≤ AVDD – 0.1 V		 ±0.5 nA
PGA enabled, gain 1 to 128,
V(AINx)MIN ≤ V(AINx) ≤ V(AINx)MAX 		–10 ±0.1 10
Differential input current PGA bypassed,
VCM = AVDD / 2, –VREF ≤ VIN ≤ VREF 		±1 nA/V
PGA enabled, gain 1 to 128,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain		 ±0.02 nA
PGA
Gain settings 1, 2, 4, 8, 16,
32, 64, 128
Startup time Enabling the PGA in conversion mode 190 µs
SYSTEM PERFORMANCE
Resolution (no missing codes) 16 Bits
DR Data rate 2.5, 5, 10, 16.6,
20, 50, 60, 100,
200, 400, 800,
1000, 2000, 4000		 SPS
INL Integral nonlinearity (best fit) PGA bypassed, VCM = AVDD / 2 1 ppmFSR
PGA enabled, gain = 1 to 128, VCM = AVDD / 2 2 25
VIO Input offset voltage PGA bypassed 20 µV
PGA enabled, gain = 1 to 8 20 / Gain
PGA enabled, gain = 16 to 128 2
PGA bypassed, after internal offset calibration On the order of noisePP at the set DR and gain
PGA enabled, gain = 1 to 128, after internal offset calibration On the order of noisePP at the set DR and gain
Offset drift PGA bypassed 10 nV/°C
PGA enabled, gain = 1 to 128 15
Gain error(1) TA = 25°C, PGA bypassed 0.01% 0.1%
TA = 25°C, PGA enabled, gain = 1 to 128   0.025% 0.2%
Gain drift(1) PGA bypassed 0.5 ppm/°C
PGA enabled, gain = 1 to 128 1
Noise (input-referred) See the Noise Performance section
NMRR Normal-mode rejection ratio(2) fIN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS 75 95 dB
fIN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS,
external fCLK = 4.096 MHz		 95
CMRR Common-mode rejection ratio At dc 120 dB
fCM = 50 Hz or 60 Hz (±1 Hz),
DR = 2.5 SPS, 5 SPS, 10 SPS, 20 SPS		 125
PSRR Power-supply rejection ratio AVDD at dc 105 dB
AVDD at 50 Hz or 60 Hz 115
DVDD at dc 115
VOLTAGE REFERENCE INPUTS
Absolute input current Reference buffers disabled, external VREF = 2.5 V,
REFP1/REFN1 inputs		 4 µA/V
Reference buffers enabled, external VREF = 2.5 V,
REFP1/REFN1 inputs		 5 nA
INTERNAL VOLTAGE REFERENCE
VREF Output voltage 2.5 V
Accuracy TA = 25°C –0.2% ±0.01% 0.2%
Temperature drift 8 40 ppm/°C
Output current AVDD = 2.7 V to 3.3 V, sink and source –5 5 mA
AVDD = 3.3 V to 5.25 V, sink and source –10 10
Short-circuit current limit Sink and source 70 100 mA
PSRR Power-supply rejection ratio AVDD at dc 85 dB
Load regulation AVDD = 2.7 V to 3.3 V,
load current = –5 mA to 5 mA		 8 µV/mA
AVDD = 3.3 V to 5.25 V,
load current = –10 mA to 10 mA		 8
Startup time 1-µF capacitor on REFOUT, 0.001% settling 5.9 ms
Capacitive load stability Capacitor on REFOUT 1 47 µF
Reference noise f = 0.1 Hz to 10 Hz, 1-µF capacitor on REFOUT 9 µVPP
INTERNAL OSCILLATOR
fCLK Frequency 4.096 MHz
Accuracy –2% 2%
EXCITATION CURRENT SOURCES (IDACS)
Current settings 10, 50, 100,
250, 500, 750,
1000, 1500, 2000		 µA
Compliance voltage(3) 10 µA to 750 µA, 0.1% deviation AVSS AVDD – 0.4 V
1 mA to 2 mA, 0.1% deviation AVSS AVDD – 0.6
Accuracy (each IDAC) TA = 25°C, 10 µA to 2 mA –6% ±1% 6%
Current mismatch between IDACs TA = 25°C, 10 µA to 2 mA 0.2%
Temperature drift (each IDAC) 10 µA to 2 mA 100 ppm/°C
Temperature drift matching between IDACs 10 µA to 2 mA 10 ppm/°C
Startup time With internal reference already settled. From end of WREG command to current flowing out of pin. 22 µs
BIAS VOLTAGE
VBIAS Output voltage (AVDD + AVSS) / 2 V
Output impedance 350 Ω
Startup time Combined capacitive load on all selected analog inputs CLOAD = 1 µF, 0.1% settling 2.8 ms
BURNOUT CURRENT SOURCES (BOCS)
Current settings 0.2, 1, 10 µA
Accuracy 0.2 µA, sinking or sourcing ±8%
1 µA, sinking or sourcing ±4%
10 µA, sinking or sourcing ±2%
EXTERNAL REFERENCE MONITOR
Threshold 0.3 V
SUPPLY VOLTAGE MONITORS
Accuracy (AVDD – AVSS) / 4 monitor ±1%
DVDD / 4 monitor ±1%
TEMPERATURE SENSOR
Output voltage TA = 25°C 129 mV
Temperature coefficient 403 µV/°C
GENERAL-PURPOSE INPUT/OUTPUTS (GPIOs)
VIL Logic input level, low AVSS – 0.05 0.3 AVDD V
VIH Logic input level, high 0.7 AVDD AVDD + 0.05 V
VOL Logic output level, low IOL = 1 mA AVSS 0.2 AVDD V
VOH Logic output level, high IOH = 1 mA 0.8 AVDD AVDD V
DIGITAL INPUT/OUTPUTS
VIL Logic input level, low DGND 0.3 IOVDD V
VIH Logic input level, high 0.7 IOVDD IOVDD V
VOL Logic output level, low IOL = 1 mA DGND 0.2 IOVDD V
VOH Logic output level, high IOH = 1 mA 0.8 IOVDD IOVDD V
Input current DGND ≤ VDigital Input ≤ IOVDD –1 1 µA
ANALOG SUPPLY CURRENT (AVDD = 3.3 V, External Reference, Internal Reference Disabled, Reference Buffers Disabled, IDACs Disabled, VBIAS Disabled, Internal Oscillator, All Data Rates, VIN = 0 V)
IAVDD Analog supply current Power-down mode 0.1 µA
Standby mode, PGA bypassed 70
Conversion mode, PGA bypassed 85
Conversion mode, PGA enabled, gain = 1, 2 120
Conversion mode, PGA enabled, gain = 4, 8 140
Conversion mode, PGA enabled, gain = 16, 32 165
Conversion mode, PGA enabled, gain = 64 200
Conversion mode, PGA enabled, gain = 128 250
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 3.3 V)
IAVDD Analog supply current Internal 2.5-V reference, no external load 185 µA
Positive reference buffer 35
Negative reference buffer 25
VBIAS buffer, no external load 10
IDAC overhead, 10 µA to 250 µA 20
IDAC overhead, 500 µA to 750 µA 30
IDAC overhead, 1 mA 40
IDAC overhead, 1.5 mA 50
IDAC overhead, 2 mA 65
Reference monitor circuit 10
DIGITAL SUPPLY CURRENT (DVDD = IOVDD = 3.3 V, All Data Rates, SPI Not Active)
IDVDD + IIOVDD Digital supply current Power-down mode, internal oscillator 0.1 µA
Standby mode, internal oscillator 185
Conversion mode, internal oscillator 225
Conversion mode, external fCLK = 4.096 MHz 195
POWER DISSIPATION (AVDD = DVDD = IOVDD = 3.3 V, Internal Reference Enabled, Reference Buffers Disabled, IDACs Disabled, VBIAS Disabled, Internal Oscillator, All Data Rates, VIN = 0 V, SPI Not Active)
PD Power dissipation Conversion mode, PGA enabled, gain = 1 1.75 mW
(1) Excluding error of voltage reference.
(2) See the 50-Hz and 60-Hz Line Cycle Rejection section for more information.
(3) The IDAC current does not change by more than 0.1% from the nominal value when staying within the specified compliance voltage.