JAJSDU5A August   2017  – February 2020 ADS114S06B , ADS114S08B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      機能ブロック図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Multiplexer
      2. 9.3.2  Low-Noise Programmable Gain Amplifier
        1. 9.3.2.1 PGA Input-Voltage Requirements
        2. 9.3.2.2 Bypassing the PGA
      3. 9.3.3  Voltage Reference
        1. 9.3.3.1 Internal Reference
        2. 9.3.3.2 External Reference
        3. 9.3.3.3 Reference Buffers
      4. 9.3.4  Clock Source
      5. 9.3.5  Delta-Sigma Modulator
      6. 9.3.6  Digital Filter
        1. 9.3.6.1 Digital Filter Frequency Response
        2. 9.3.6.2 Data Conversion Time
        3. 9.3.6.3 Note on Conversion Time
        4. 9.3.6.4 50-Hz and 60-Hz Line Cycle Rejection
      7. 9.3.7  Excitation Current Sources (IDACs)
      8. 9.3.8  Bias Voltage Generation
      9. 9.3.9  System Monitor
        1. 9.3.9.1 Internal Temperature Sensor
        2. 9.3.9.2 Power Supply Monitors
        3. 9.3.9.3 Burn-Out Current Sources
      10. 9.3.10 Status Register
        1. 9.3.10.1 POR Flag
        2. 9.3.10.2 RDY Flag
        3. 9.3.10.3 External Reference Monitor
      11. 9.3.11 General-Purpose Inputs and Outputs (GPIOs)
      12. 9.3.12 Calibration
        1. 9.3.12.1 Offset Calibration
        2. 9.3.12.2 Gain Calibration
    4. 9.4 Device Functional Modes
      1. 9.4.1 Reset
        1. 9.4.1.1 Power-On Reset
        2. 9.4.1.2 RESET Pin
        3. 9.4.1.3 Reset by Command
      2. 9.4.2 Power-Down Mode
      3. 9.4.3 Standby Mode
      4. 9.4.4 Conversion Modes
        1. 9.4.4.1 Continuous Conversion Mode
        2. 9.4.4.2 Single-Shot Conversion Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Serial Data Input (DIN)
        4. 9.5.1.4 Serial Data Output and Data Ready (DOUT/DRDY)
        5. 9.5.1.5 Data Ready (DRDY)
        6. 9.5.1.6 Timeout
      2. 9.5.2 Data Format
      3. 9.5.3 Commands
        1. 9.5.3.1  NOP
        2. 9.5.3.2  WAKEUP
        3. 9.5.3.3  POWERDOWN
        4. 9.5.3.4  RESET
        5. 9.5.3.5  START
        6. 9.5.3.6  STOP
        7. 9.5.3.7  SYOCAL
        8. 9.5.3.8  SYGCAL
        9. 9.5.3.9  SFOCAL
        10. 9.5.3.10 RDATA
        11. 9.5.3.11 RREG
        12. 9.5.3.12 WREG
      4. 9.5.4 Interfacing with Multiple Devices
    6. 9.6 Register Map
      1. 9.6.1 Configuration Registers
      2. 9.6.2 Register Descriptions
        1. 9.6.2.1  Device ID Register (address = 00h) [reset = xxh]
          1. Table 16. Device ID (ID) Register Field Descriptions
        2. 9.6.2.2  Device Status Register (address = 01h) [reset = 80h]
          1. Table 17. Device Status (STATUS) Register Field Descriptions
        3. 9.6.2.3  Input Multiplexer Register (address = 02h) [reset = 01h]
          1. Table 18. Input Multiplexer (INPMUX) Register Field Descriptions
        4. 9.6.2.4  Gain Setting Register (address = 03h) [reset = 00h]
          1. Table 19. Gain Setting (PGA) Register Field Descriptions
        5. 9.6.2.5  Data Rate Register (address = 04h) [reset = 14h]
          1. Table 20. Data Rate (DATARATE) Register Field Descriptions
        6. 9.6.2.6  Reference Control Register (address = 05h) [reset = 10h]
          1. Table 21. Reference Control (REF) Register Field Descriptions
        7. 9.6.2.7  Excitation Current Register 1 (address = 06h) [reset = 00h]
          1. Table 22. Excitation Current Register 1 (IDACMAG) Register Field Descriptions
        8. 9.6.2.8  Excitation Current Register 2 (address = 07h) [reset = FFh]
          1. Table 23. Excitation Current Register 2 (IDACMUX) Register Field Descriptions
        9. 9.6.2.9  Sensor Biasing Register (address = 08h) [reset = 00h]
          1. Table 24. Sensor Biasing (VBIAS) Register Field Descriptions
        10. 9.6.2.10 System Control Register (address = 09h) [reset = 10h]
          1. Table 25. System Control (SYS) Register Field Descriptions
        11. 9.6.2.11 Reserved Register (address = 0Ah) [reset = 00h]
          1. Table 26. Reserved Register Field Descriptions
        12. 9.6.2.12 Offset Calibration Register 1 (address = 0Bh) [reset = 00h]
          1. Table 27. Offset Calibration Register 1 (OFCAL0) Register Field Descriptions
        13. 9.6.2.13 Offset Calibration Register 2 (address = 0Ch) [reset = 00h]
          1. Table 28. Offset Calibration Register 2 (OFCAL1) Register Field Descriptions
        14. 9.6.2.14 Reserved Register (address = 0Dh) [reset = 00h]
          1. Table 29. Reserved Register Field Descriptions
        15. 9.6.2.15 Gain Calibration Register 1 (address = 0Eh) [reset = 00h]
          1. Table 30. Gain Calibration Register 1 (FSCAL0) Field Descriptions
        16. 9.6.2.16 Gain Calibration Register 2 (address = 0Fh) [reset = 40h]
          1. Table 31. Gain Calibration Register 2 (FSCAL1) Field Descriptions
        17. 9.6.2.17 GPIO Data Register (address = 10h) [reset = 00h]
          1. Table 32. GPIO Data (GPIODAT) Register Field Descriptions
        18. 9.6.2.18 GPIO Configuration Register (address = 11h) [reset = 00h]
          1. Table 33. GPIO Configuration (GPIOCON) Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Serial Interface Connections
      2. 10.1.2 Analog Input Filtering
      3. 10.1.3 External Reference and Ratiometric Measurements
      4. 10.1.4 Establishing a Proper Input Voltage
      5. 10.1.5 Unused Inputs and Outputs
      6. 10.1.6 Pseudo Code Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Register Settings
      3. 10.2.3 Application Curves
    3. 10.3 What To Do and What Not To Do
  11. 11Power Supply Recommendations
    1. 11.1 Power Supplies
    2. 11.2 Power-Supply Sequencing
    3. 11.3 Power-On Reset
    4. 11.4 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 関連リンク
    4. 13.4 ドキュメントの更新通知を受け取る方法
    5. 13.5 コミュニティ・リソース
    6. 13.6 商標
    7. 13.7 静電気放電に関する注意事項
    8. 13.8 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHB|32
  • PBS|32
サーマルパッド・メカニカル・データ
発注情報

9.3.6.3 Note on Conversion Time

Each data period consists of time required for the modulator to sample the analog inputs. However, there is additional time required before the samples become an ADC conversion result.

When a new conversion is started, there is a configuration delay time of 14 · tMOD (where tMOD = 16 · tCLK) that is added before the conversion starts. This delay allows for additional settling time for external RC filters on the analog inputs and for the antialiasing filter after the PGA. The configuration delay occurs at the start of a new conversion after a START command is sent, the START/SYNC pin is taken high, or a WREG command is sent to change any configuration register from address 03h to 07h (as described in the WREG section).

Also, overhead time is needed to convert the modulator samples into an ADC conversion result. This overhead time includes any necessary offset or gain compensation after the digital filter accumulates a data result. The first conversion when the device is in continuous conversion mode (just as in single-shot conversion mode) includes the configuration delay, the modulator sampling time, and the overhead time. The second and subsequent conversions are the normal data period (period as given by the inverse of the data rate).

Figure 62 shows the time sequence for the ADC in both continuous conversion and single-shot conversion modes.

ADS114S06B ADS114S08B ai_conv_time_sbas852.gif
1. Conversions start at the rising edge of the START/SYNC pin or on the seventh SCLK falling edge for a START command.
Figure 62. Single-Shot Conversion Mode and Continuous Conversion Mode Sequences