over recommended operating free-air temperature range at –40°C to +105°C, AVDD = 5 V, and BVDD = 5 V (unless otherwise noted)
MIN
MAX
UNIT
tC1
CLKIN period
31.25
1000
ns
tW1
CLKIN high time
10
tC1 – 10
ns
tC2
CLKOUT period using internal oscillator (CLKSEL = 1)
83
125
ns
CLKOUT period using external clock (CLKSEL = 0)
2 × tC1
ns
tW2
CLKOUT high time
(tC2 / 2) – 5
(tC2 / 2) + 5
ns
tD1
CLKOUT rising edge delay after CLKIN rising edge
0
10
ns
tD2
CLKOUT falling edge delay after CLKIN rising edge
0
10
ns
tD3
Data valid delay after rising edge of CLKOUT (CLKSEL = 1)
(tC2 / 4) – 8
(tC2 / 4) + 8
ns
tD4
Data valid delay after rising edge of CLKOUT (CLKSEL = 0)
tW1 – 3
tW1 + 7
ns
(1) Applicable for 5.0-V nominal supply: BVDD (min) = 4.5 V and BVDD (max) = 5.5 V. All input signals are specified with tR = tF = 5 ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH) / 2. See Figure 1.