JAJSI32
October 2019
ADS1235-Q1
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
Device Images
ブロック図
ADC変換ノイズ
4
改訂履歴
5
概要(続き)
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Switching Characteristics
7.8
Typical Characteristics
8
Parameter Measurement Information
8.1
Noise Performance
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Analog Inputs
9.3.1.1
ESD Diodes
9.3.1.2
Input Multiplexer
9.3.1.3
Temperature Sensor
9.3.1.4
Inputs Open
9.3.1.5
Internal VCOM Connection
9.3.1.6
Alternate Functions
9.3.2
PGA
9.3.2.1
Input Voltage Range
9.3.2.2
PGA Bypass Mode
9.3.3
PGA Voltage Monitor
9.3.4
Reference Voltage
9.3.4.1
External Reference
9.3.4.2
AVDD – AVSS Reference (Default)
9.3.4.3
Reference Monitor
9.3.5
General-Purpose Input/Outputs (GPIOs)
9.3.6
Modulator
9.3.7
Digital Filter
9.3.7.1
Sinc Filter
9.3.7.1.1
Sinc Filter Frequency Response
9.3.7.2
FIR Filter
9.3.7.2.1
FIR Filter Frequency Response
9.3.7.3
Filter Bandwidth
9.3.7.4
50-Hz and 60-Hz Normal Mode Rejection
9.4
Device Functional Modes
9.4.1
Conversion Control
9.4.1.1
Continuous-Conversion Mode
9.4.1.2
Pulse-Conversion Mode
9.4.1.3
Conversion Latency
9.4.1.4
Start-Conversion Delay
9.4.2
Chop Mode
9.4.3
AC-Bridge Excitation Mode
9.4.4
ADC Clock Mode
9.4.5
Power-Down Mode
9.4.5.1
Hardware Power-Down
9.4.5.2
Software Power-Down
9.4.6
Reset
9.4.6.1
Power-on Reset
9.4.6.2
Reset by Pin
9.4.6.3
Reset by Command
9.4.7
Calibration
9.4.7.1
Offset and Full-Scale Calibration
9.4.7.1.1
Offset Calibration Registers
9.4.7.1.2
Full-Scale Calibration Registers
9.4.7.2
Offset Self-Calibration (SFOCAL)
9.4.7.3
Offset System-Calibration (SYOCAL)
9.4.7.4
Full-Scale Calibration (GANCAL)
9.4.7.5
Calibration Command Procedure
9.4.7.6
User Calibration Procedure
9.5
Programming
9.5.1
Serial Interface
9.5.1.1
Chip Select (CS)
9.5.1.2
Serial Clock (SCLK)
9.5.1.3
Data Input (DIN)
9.5.1.4
Data Output/Data Ready (DOUT/DRDY)
9.5.1.5
Serial Interface Auto-Reset
9.5.2
Data Ready (DRDY)
9.5.2.1
DRDY in Continuous-Conversion Mode
9.5.2.2
DRDY in Pulse-Conversion Mode
9.5.2.3
Data Ready by Software Polling
9.5.3
Conversion Data
9.5.3.1
Status byte (STATUS)
9.5.3.2
Conversion Data Format
9.5.4
CRC
9.5.5
Commands
9.5.5.1
NOP Command
9.5.5.2
RESET Command
9.5.5.3
START Command
9.5.5.4
STOP Command
9.5.5.5
RDATA Command
9.5.5.6
SYOCAL Command
9.5.5.7
GANCAL Command
9.5.5.8
SFOCAL Command
9.5.5.9
RREG Command
9.5.5.10
WREG Command
9.5.5.11
LOCK Command
9.5.5.12
UNLOCK Command
9.6
Register Map
9.6.1
Device Identification (ID) Register (address = 00h) [reset = Cxh]
Table 28.
ID Register Field Descriptions
9.6.2
Device Status (STATUS) Register (address = 01h) [reset = 01h]
Table 29.
STATUS Register Field Descriptions
9.6.3
Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
Table 30.
MODE0 Register Field Descriptions
9.6.4
Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
Table 31.
MODE1 Register Field Descriptions
9.6.5
Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
Table 32.
MODE2 Register Field Descriptions
9.6.6
Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
Table 33.
MODE3 Register Field Descriptions
9.6.7
Reference Configuration (REF) Register (address = 06h) [reset = 05h]
Table 34.
REF Register Field Descriptions
9.6.8
Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
Table 35.
OFCAL0, OFCAL1, OFCAL2 Registers Field Description
9.6.9
Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
Table 36.
FSCAL0, FSCAL1, FSCAL2 Registers Field Description
9.6.10
Reserved (RESERVED) Register (address = 0Dh) [reset = FFh]
Table 37.
RESERVED Register Field Descriptions
9.6.11
Reserved (RESERVED) Register (address = 0Eh) [reset = 00h]
Table 38.
RESERVED Register Field Descriptions
9.6.12
Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
Table 39.
RESERVED Register Field Descriptions
9.6.13
PGA Configuration (PGA) Register (address = 10h) [reset = 00h]
Table 40.
PGA Register Field Descriptions
9.6.14
Input Multiplexer (INPMUX) Register (address = 11h) [reset = FFh]
Table 41.
INPMUX Register Field Descriptions
10
Application and Implementation
10.1
Application Information
10.1.1
Input Range
10.1.2
Input Overload
10.1.3
Unused Inputs and Outputs
10.1.4
Multiplexed 2-Bridge Input Example
10.1.5
AC-Bridge Excitation Example
10.1.6
Serial Interface and Digital Connections
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.3
Application Curves
10.3
Initialization Setup
11
Power Supply Recommendations
11.1
Power-Supply Decoupling
11.2
Analog Power-Supply Clamp
11.3
Power-Supply Sequencing
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
デバイスおよびドキュメントのサポート
13.1
ドキュメントのサポート
13.1.1
関連資料
13.2
ドキュメントの更新通知を受け取る方法
13.3
コミュニティ・リソース
13.4
商標
13.5
静電気放電に関する注意事項
13.6
Glossary
14
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHM|32
MPQF152B
サーマルパッド・メカニカル・データ
RHM|32
QFND568
発注情報
jajsi32_oa
1
特長
車載アプリケーション用に AEC-Q100 認定済み
温度グレード 1: -40℃~+125℃、T
A
24 ビット、高精度 ADC
ノイズフリー・カウント:120,000
(10mV 入力、10SPS)
オフセット・ドリフト係数: 1nV/℃
ゲイン・ドリフト係数: 0.5ppm/℃
3 つの差動または 5 つのシングルエンド入力
2 つの基準電圧入力
広い入力電圧範囲:±7mV~±5V
低ノイズ PGA、ゲイン:1、64、128
データ・レート:2.5SPS~7200SPS
AC または DC ブリッジ励起オプション
チョップ・モードによりゼロドリフト動作を実現
50Hz/60Hz 同時除去モード
シングルサイクル・セトリング・モード
基準電圧入力喪失モニタ
信号オーバーレンジ・モニタ
温度センサ
巡回冗長性検査 (CRC)
5V または ±2.5V 電源