JAJSHL9A June   2019  – January 2021 ADS125H01

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Noise Performance
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage Range
      2. 9.3.2 Analog Inputs (AINP, AINN)
        1. 9.3.2.1 ESD Diodes
        2. 9.3.2.2 Input Switch
      3. 9.3.3 Programmable Gain Amplifier (PGA)
        1. 9.3.3.1 PGA Operating Range
        2. 9.3.3.2 PGA Monitors
      4. 9.3.4 Reference Voltage
        1. 9.3.4.1 Reference Monitor
      5. 9.3.5 ADC Modulator
      6. 9.3.6 Digital Filter
        1. 9.3.6.1 Sinc Filter Mode
          1. 9.3.6.1.1 Sinc Filter Frequency Response
        2. 9.3.6.2 FIR Filter
        3. 9.3.6.3 50-Hz and 60-Hz Normal-Mode Rejection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Conversion Control
        1. 9.4.1.1 Continuous-Conversion Mode
        2. 9.4.1.2 Pulse-Conversion Mode
        3. 9.4.1.3 Conversion Latency
        4. 9.4.1.4 Start-Conversion Delay
      2. 9.4.2 Clock Mode
      3. 9.4.3 Reset
        1. 9.4.3.1 Power-On Reset
        2. 9.4.3.2 Reset by RESETPin
        3. 9.4.3.3 Reset by Command
      4. 9.4.4 Calibration
        1. 9.4.4.1 Offset and Full-Scale Calibration
          1. 9.4.4.1.1 Offset Calibration Registers
          2. 9.4.4.1.2 Full-Scale Calibration Registers
        2. 9.4.4.2 Offset Calibration Command (OFSCAL)
        3. 9.4.4.3 Full-Scale Calibration Command (GANCAL)
        4. 9.4.4.4 Calibration Command Procedure
        5. 9.4.4.5 User Calibration Procedure
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip-Select Pins (CS1 and CS2)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output/Data Ready (DOUT/DRDY)
      2. 9.5.2 Data Ready (DRDY)
        1. 9.5.2.1 DRDY in Continuous-Conversion Mode
        2. 9.5.2.2 DRDY in Pulse-Conversion Mode
        3. 9.5.2.3 Data Ready by Software Polling
      3. 9.5.3 Conversion Data
        1. 9.5.3.1 Status Byte (STATUS0)
        2. 9.5.3.2 Conversion Data Format
      4. 9.5.4 Cyclic Redundancy Check (CRC)
      5. 9.5.5 Commands
        1. 9.5.5.1  General Command Format
        2. 9.5.5.2  NOP Command
        3. 9.5.5.3  RESET Command
        4. 9.5.5.4  START Command
        5. 9.5.5.5  STOP Command
        6. 9.5.5.6  RDATA Command
        7. 9.5.5.7  OFSCAL Command
        8. 9.5.5.8  GANCAL Command
        9. 9.5.5.9  RREG Command
        10. 9.5.5.10 WREG Command
    6. 9.6 Register Map
      1. 9.6.1  Device Identification (ID) Register (address = 00h) [reset = 4xh]
      2. 9.6.2  Main Status (STATUS0) Register (address = 01h) [reset = 01h]
      3. 9.6.3  Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
      4. 9.6.4  Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
      5. 9.6.5  Reserved (RESERVED) Register (address = 04h) [reset = 00h]
      6. 9.6.6  Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
      7. 9.6.7  Reference Configuration (REF) Register (address = 06h) [reset = 05h]
      8. 9.6.8  Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
      9. 9.6.9  Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
      10. 9.6.10 Reserved (RESERVED) Register (address = 0Dh) [reset = FFh]
      11. 9.6.11 Reserved (RESERVED) Register (address = 0Eh) [reset = 00h]
      12. 9.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
      13. 9.6.13 MODE4 (MODE4) Register (address = 10h) [reset = 50h]
      14. 9.6.14 PGA Alarm (STATUS1) Register (address = 11h) [reset = xxh]
      15. 9.6.15 Status 2 (STATUS2) Register (address = 12h) [reset = 0xh]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Example to Determine the PGA Linear Operating Range
      2. 10.1.2 Input Signal Rate of Change (dV/dt)
      3. 10.1.3 Unused Inputs and Outputs
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Noise Performance

Noise performance depends on the device configuration: data rate, input gain, and digital filter mode. Two significant factors affecting noise performance are data rate and input gain. Decreasing the data rate lowers the noise because the measurement bandwidth is reduced. Increasing the gain reduces noise (when noise is treated as an input-referred quantity) because the noise of the PGA is lower than that of the ADC. Noise performance also depends on the digital filter mode. As the digital filter order is increased, the bandwidth decreases, which results in lower noise.

Figure 8-1 shows noise data versus data rate as input-referred values (µVRMS) in gains 0.125 to 2, (corresponding input ranges of ±20 V to ±1.25 V) in the sinc3 filter mode. Figure 8-2 shows noise data versus data rate as input-referred values (µVRMS) in gains 4 to 128, (corresponding input ranges of ±625 mV to ±19.5 mV) in the sinc3 filter mode. The noise data represent typical ADC performance at TA = 25°C and the 2.5-V reference voltage.

Peak-to-peak noise performance is typically 6.6 times the RMS value. Relative to the noise in the sinc3 filter mode, noise typically increases 30% in the finite-impulse response (FIR) and sinc1 filter mode because of the increased bandwidth of the sinc1 and FIR modes. Noise typically decreases 6% in the sinc4 filter mode because of the decreased bandwidth of the sinc4 filter mode.

The noise data are the standard deviation of the ADC data scaled in microvolts. The data are acquired with inputs shorted and based on consecutive ADC readings for a period of ten seconds or 8192 data points, whichever occurs first. Because of the statistical nature of noise, repeated measurements may yield higher or lower noise results.

GUID-FEE14649-70DE-4381-9961-B28EF80C6F66-low.gif
Gain = 0.125 to 2, VREF = 2.5 V, sinc3 filter
(sinc5 filter for fDATA ≥ 14.4 kSPS)
Figure 8-1 Conversion Noise vs Data Rate
GUID-4AF2128E-2392-490F-B948-193575084D8B-low.gif
Gain = 4 to 128, VREF = 2.5 V, sinc3 filter
(sinc5 filter for fDATA ≥ 14.4 kSPS)
Figure 8-2 Conversion Noise vs Data Rate

ADC noise performance can also be expressed as effective resolution and noise-free resolution (bits). Effective resolution is based on the RMS value of the noise data and noise-free resolution is based on the peak-to-peak noise data; therefore, the noise-free resolution is the resolution with no code flicker. Equation 1 is used to compute effective resolution based on the noise values plots of Figure 8-1 and Figure 8-2.

Equation 1. Effective Resolution or Noise-Free Resolution (Bits) = 3.32 log (FSR / en)

where:

  • FSR = Full-scale range = 2 VREF / Gain
  • en = Input-referred noise (RMS value for effective resolution, peak-to-peak value for noise-free resolution)

For example, using full-scale range = ±13.3 V, data rate = 20 SPS, and sinc3 filter mode, the RMS noise value (from Figure 8-1) is 2.1 µV. The effective resolution is: 3.32 log (26.6 V / 2.1 µV) = 23.6 bits.

Figure 8-3 and Figure 8-4 show effective resolution (bits) versus data rate. Figure 8-5 and Figure 8-6 show noise-free resolution (bits) versus data rate. When fDATA ≤ 14.4 kSPS, effective resolution and noise-free resolution improve by 0.7 bits by increasing the reference voltage from 2.5 V to 4.096 V because of the increased input signal range.

GUID-9C71DCA8-68A6-4DCA-85B4-6671CE55EA83-low.gif
Gain = 0.125 to 2, VREF = 2.5 V, sinc3 filter
(sinc5 filter for fDATA ≥ 14.4 kSPS)
Figure 8-3 Effective Resolution vs Data Rate
GUID-344E9710-1110-4329-8392-DBE07F7CC3FB-low.gif
Gain = 0.125 to 2, VREF = 2.5 V, sinc3 filter
(sinc5 filter for fDATA ≥ 14.4 kSPS)
Figure 8-5 Noise-Free Resolution vs Data Rate
GUID-B330AB35-741C-4BAC-8E52-59D56030B201-low.gif
Gain = 4 to 128, VREF = 2.5 V, sinc3 filter mode
(sinc5 filter for fDATA ≥ 14.4 kSPS)
Figure 8-4 Effective Resolution vs Data Rate
GUID-ED204CC2-E796-426E-A863-3E947E01A056-low.gif
Gain = 4 to 128, VREF = 2.5 V, sinc3 filter
(sinc5 filter for fDATA ≥ 14.4 kSPS)
Figure 8-6 Noise-Free Resolution vs Data Rate