The PGA is a low-noise, programmable gain (attenuation), CMOS differential-input, differential-output amplifier. The PGA operates in gain or attenuation mode depending on the selected gain. Typically, the PGA is programmed for gain when the expected input signal voltage is ≤ V_REF and is programmed for attenuation when the expected input signal voltage is ≥ V_REF.

Figure 9-1 shows the block diagram of the PGA.

Figure 9-1 PGA Block Diagram

The signal inputs are RC filtered to reduce sensitivity to radio frequency interference (RFI) and electromagnetic interference (EMI). The first PGA stage is a high input-impedance, noninverting differential amplifier (amplifiers A1 and A2) and provides gain. Inverse-parallel connected diodes across the inputs of A1 and A2 clamp the amplifier input voltage if they are driven out-of-range. If the amplifier is out-of-range, the diodes can conduct, resulting in current flow through the analog input pins. High dV/dt input signals, such as those generated from the switching of a multiplexer, can lead to transient turn-on of the clamp diodes. In some cases, an RC filter at the PGA inputs may be necessary to limit the dV/dt of the signal to prevent the clamp diodes from turning on.

The second stage (amplifiers A3 and A4) is an inverting, differential amplifier. This stage provides attenuation of high-amplitude signal levels. The common-mode voltage of this stage is AVDD / 2. The second stage drives the modulator input of the ADC and is also connected to the CAPP and CAPN pins. An external 1-nF capacitor filters the modulator input sample pulses and also provides the antialias filter for the ADC. Place the capacitor close to the pins using short, direct traces. Avoid running clock traces or other digital traces underneath or in the vicinity of these pins. Gain is programmed by the GAIN[3:0] bits of the MODE 4 register.

Monitors verify the voltage headroom of the PGA input and output nodes. See the Section 9.3.3.2 section for details.