JAJSHL9A June   2019  – January 2021 ADS125H01

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input Voltage Range
      2. 9.3.2 Analog Inputs (AINP, AINN)
        1. 9.3.2.1 ESD Diodes
        2. 9.3.2.2 Input Switch
      3. 9.3.3 Programmable Gain Amplifier (PGA)
        1. 9.3.3.1 PGA Operating Range
        2. 9.3.3.2 PGA Monitors
      4. 9.3.4 Reference Voltage
        1. 9.3.4.1 Reference Monitor
      5. 9.3.5 ADC Modulator
      6. 9.3.6 Digital Filter
        1. 9.3.6.1 Sinc Filter Mode
          1. 9.3.6.1.1 Sinc Filter Frequency Response
        2. 9.3.6.2 FIR Filter
        3. 9.3.6.3 50-Hz and 60-Hz Normal-Mode Rejection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Conversion Control
        1. 9.4.1.1 Continuous-Conversion Mode
        2. 9.4.1.2 Pulse-Conversion Mode
        3. 9.4.1.3 Conversion Latency
        4. 9.4.1.4 Start-Conversion Delay
      2. 9.4.2 Clock Mode
      3. 9.4.3 Reset
        1. 9.4.3.1 Power-On Reset
        2. 9.4.3.2 Reset by RESETPin
        3. 9.4.3.3 Reset by Command
      4. 9.4.4 Calibration
        1. 9.4.4.1 Offset and Full-Scale Calibration
          1. 9.4.4.1.1 Offset Calibration Registers
          2. 9.4.4.1.2 Full-Scale Calibration Registers
        2. 9.4.4.2 Offset Calibration Command (OFSCAL)
        3. 9.4.4.3 Full-Scale Calibration Command (GANCAL)
        4. 9.4.4.4 Calibration Command Procedure
        5. 9.4.4.5 User Calibration Procedure
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip-Select Pins (CS1 and CS2)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output/Data Ready (DOUT/DRDY)
      2. 9.5.2 Data Ready (DRDY)
        1. 9.5.2.1 DRDY in Continuous-Conversion Mode
        2. 9.5.2.2 DRDY in Pulse-Conversion Mode
        3. 9.5.2.3 Data Ready by Software Polling
      3. 9.5.3 Conversion Data
        1. 9.5.3.1 Status Byte (STATUS0)
        2. 9.5.3.2 Conversion Data Format
      4. 9.5.4 Cyclic Redundancy Check (CRC)
      5. 9.5.5 Commands
        1. 9.5.5.1  General Command Format
        2. 9.5.5.2  NOP Command
        3. 9.5.5.3  RESET Command
        4. 9.5.5.4  START Command
        5. 9.5.5.5  STOP Command
        6. 9.5.5.6  RDATA Command
        7. 9.5.5.7  OFSCAL Command
        8. 9.5.5.8  GANCAL Command
        9. 9.5.5.9  RREG Command
        10. 9.5.5.10 WREG Command
    6. 9.6 Register Map
      1. 9.6.1  Device Identification (ID) Register (address = 00h) [reset = 4xh]
      2. 9.6.2  Main Status (STATUS0) Register (address = 01h) [reset = 01h]
      3. 9.6.3  Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
      4. 9.6.4  Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
      5. 9.6.5  Reserved (RESERVED) Register (address = 04h) [reset = 00h]
      6. 9.6.6  Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
      7. 9.6.7  Reference Configuration (REF) Register (address = 06h) [reset = 05h]
      8. 9.6.8  Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
      9. 9.6.9  Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
      10. 9.6.10 Reserved (RESERVED) Register (address = 0Dh) [reset = FFh]
      11. 9.6.11 Reserved (RESERVED) Register (address = 0Eh) [reset = 00h]
      12. 9.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
      13. 9.6.13 MODE4 (MODE4) Register (address = 10h) [reset = 50h]
      14. 9.6.14 PGA Alarm (STATUS1) Register (address = 11h) [reset = xxh]
      15. 9.6.15 Status 2 (STATUS2) Register (address = 12h) [reset = 0xh]
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Example to Determine the PGA Linear Operating Range
      2. 10.1.2 Input Signal Rate of Change (dV/dt)
      3. 10.1.3 Unused Inputs and Outputs
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
9.3.6.1.1 Sinc Filter Frequency Response

As shown in Figure 9-7 and Figure 9-8, the first-stage sinc5 filter has frequency response nulls occurring at N × fDATA (where N = 1, 2, 3, and so on). At the null frequencies, the filter has zero gain.

GUID-AF6E369E-E366-4400-8076-E2FC58075010-low.gifFigure 9-7 Sinc5 Filter Frequency Response       (40 kSPS)
GUID-111C3629-610C-457E-B190-2A1B2CB4A71C-low.gifFigure 9-8 Sinc5 Filter Frequency Response     (14.4 kSPS)

The second stage filter superimposes additional nulls to the nulls produced by the first stage. The first of the nulls occurs at the output data rate with additional nulls occurring at data rate multiples.

Figure 9-9 shows the frequency response at 2.4 kSPS. This data rate has five equally spaced nulls between the first stage 14.4-kHz nulls [(14.4 kHz / 2.4 kHz) – 1 = 5]. This frequency response is similar to that of data rates 2.5 SPS to 7.2 kSPS. Figure 9-10 shows the frequency response nulls at 10 SPS.

GUID-EAF029A7-C853-4600-9475-B0EA2F0D306D-low.gifFigure 9-9 Sinc Filter Frequency Response       (2400 SPS)
GUID-E0F7C4A9-CA38-4785-9FD2-CE6F1B60E78E-low.gifFigure 9-10 Sinc Filter Frequency Response       (10 SPS)

Figure 9-11 and Figure 9-12 show the frequency response of data rates 50 SPS and 60 SPS. 50-Hz or 60-Hz rejection is increased by increasing the order of the sinc filter.

GUID-86F89359-EEB3-44AE-91E5-C3856E4EE5DF-low.gifFigure 9-11 Sinc Filter Frequency Response       (50 SPS)
GUID-FADF47B4-7489-4075-8832-25A1D2F000EC-low.gifFigure 9-12 Sinc Filter Frequency Response       (60 SPS)

Figure 9-13 and Figure 9-14 show the detailed frequency response of the 50-SPS and 60-SPS data rates.

GUID-5A7C7A3C-4056-4C94-BA96-D0E468FC593D-low.gifFigure 9-13 Sinc Filter Frequency Response       (50 SPS)
GUID-C9AE42DC-4151-4C74-A6B5-F0315FA85EE7-low.gifFigure 9-14 Sinc Filter Frequency Response       (60 SPS)

The sinc filter has an overall low-pass response that rolls off high-frequency components of the signal. The filter bandwidth depends on the output data rate and the filter order. The system bandwidth is the combined bandwidths of the digital filter, the PGA antialias filter, and external signal filters. Table 9-3 lists the –3-dB bandwidth of the sinc filter.

Table 9-3 Sinc Filter Bandwidth
–3-dB BANDWIDTH (Hz)
DATA RATE (SPS) SINC1 SINC3 SINC4 SINC5
2.5 1.10 0.65 0.58 —
5 2.23 1.33 1.15 —
10 4.43 2.62 2.28 —
16.6 7.38 4.37 3.80 —
20 8.85 5.25 4.63 —
50 22.1 13.1 11.4 —
60 26.6 15.7 13.7 —
100 44.3 26.2 22.8 —
400 177 105 91.0 —
1200 525 314 273 —
2400 1015 623 544 —
4800 1798 1214 1077 —
7200 2310 1750 1590 —
14400 — — — 2940
19200 — — — 3920
25600 — — — 5227
40000 — — — 8167