JAJSGG2C October 2018 – June 2019 ADS125H02
PRODUCTION DATA.
STATUS1 is shown in Figure 95 and described in Table 43.
Return to Register Map Summary.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PGA_ONL | PGA_ONH | PGA_OPL | PGA_OPH | PGA_INL | PGA_INH | PGA_IPL | PGA_IPH |
R-xxh |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PGA_ONL | R | xh |
PGA Output Negative Low Alarm This bit is cleared on register read (clear-on-read). 0: No alarm 1: Alarm active |
6 | PGA_ONH | R | xh |
PGA Output Negative High Alarm This bit is cleared on register read (clear-on-read).0: No alarm 1: Alarm active |
5 | PGA_OPL | R | xh |
PGA Output Positive Low Alarm This bit is cleared on register read (clear-on-read).0: No alarm 1: Alarm active |
4 | PGA_OPH | R | xh |
PGA Output Positive High Alarm This bit is cleared on register read (clear-on-read).0: No alarm 1: Alarm active |
3 | PGA_INL | R | xh |
PGA Input Negative Low Alarm This bit is cleared on register read (clear-on-read).0: No alarm 1: Alarm active |
2 | PGA_INH | R | xh |
PGA Input Negative High Alarm This bit is cleared on register read (clear-on-read).0: No alarm 1: Alarm active |
1 | PGA_IPL | R | xh |
PGA Input Positive Low Alarm This bit is cleared on register read (clear-on-read).0: No alarm 1: Alarm active |
0 | PGA_IPH | R | xh |
PGA Input Positive High Alarm This bit is cleared on register read (clear-on-read).0: No alarm 1: Alarm active |