JAJSGG2C
October 2018 – June 2019
ADS125H02
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
機能ブロック図
4
改訂履歴
5
概要(続き)
6
Device Comparison Table
7
Pin Configuration and Functions
Pin Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Switching Characteristics
8.8
Typical Characteristics
9
Parameter Measurement Information
9.1
Noise Performance
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
Input Range
10.3.2
Analog Inputs
10.3.2.1
ESD Diodes
10.3.2.2
Input Multiplexer
10.3.2.2.1
Analog Inputs (AIN0, AIN1, AINCOM)
10.3.2.2.2
High-Voltage Power Supply Readback
10.3.2.2.3
Internal VCOM Connection (Default)
10.3.2.2.4
Temperature Sensor
10.3.3
Programmable Gain Amplifier (PGA)
10.3.3.1
PGA Operating Range
10.3.3.2
PGA Monitor
10.3.4
Reference Voltage
10.3.4.1
Internal Reference
10.3.4.2
External Reference
10.3.4.3
AVDD Power-Supply Reference
10.3.4.4
Reference Monitor
10.3.5
Current Sources (IDAC1 and IDAC2)
10.3.6
General-Purpose Inputs and Outputs (GPIOs)
10.3.7
ADC Modulator
10.3.8
Digital Filter
10.3.8.1
Sinc Filter Mode
10.3.8.1.1
Sinc Filter Frequency Response
10.3.8.2
FIR Filter
10.3.8.3
50-Hz and 60-Hz Normal Mode Rejection
10.4
Device Functional Modes
10.4.1
Conversion Control
10.4.1.1
Continuous-Conversion Mode
10.4.1.2
Pulse-Conversion Mode
10.4.1.3
Conversion Latency
10.4.1.4
Start-Conversion Delay
10.4.2
Auto-Zero Mode
10.4.3
Clock Mode
10.4.4
Reset
10.4.4.1
Power-On Reset
10.4.4.2
Reset by Pin
10.4.4.3
Reset by Command
10.4.5
Calibration
10.4.5.1
Offset and Full-Scale Calibration
10.4.5.1.1
Offset Calibration Registers
10.4.5.1.2
Full-Scale Calibration Registers
10.4.5.2
Offset Calibration (OFSCAL)
10.4.5.3
Full-Scale Calibration (GANCAL)
10.4.5.4
Calibration Command Procedure
10.4.5.5
User Calibration Procedure
10.5
Programming
10.5.1
Serial Interface
10.5.1.1
Chip-Select Pins (CS1 and CS2)
10.5.1.2
Serial Clock (SCLK)
10.5.1.3
Data Input (DIN)
10.5.1.4
Data Output/Data Ready (DOUT/DRDY)
10.5.2
Data Ready (DRDY)
10.5.2.1
DRDY in Continuous-Conversion Mode
10.5.2.2
DRDY in Pulse-Conversion Mode
10.5.2.3
Data Ready by Software Polling
10.5.3
Conversion Data
10.5.3.1
Status Byte (STATUS0)
10.5.3.2
Conversion Data Format
10.5.4
Cyclic Redundancy Check (CRC)
10.5.5
Commands
10.5.5.1
General Command Format
10.5.5.2
NOP Command
10.5.5.3
RESET Command
10.5.5.4
START Command
10.5.5.5
STOP Command
10.5.5.6
RDATA Command
10.5.5.7
OFSCAL Command
10.5.5.8
GANCAL Command
10.5.5.9
RREG Command
10.5.5.10
WREG Command
10.5.5.11
LOCK Command
10.5.5.12
UNLOCK Command
10.6
Register Map
10.6.1
Device Identification (ID) Register (address = 00h) [reset = 6xh]
Table 30.
ID Register Field Descriptions
10.6.2
Main Status (STATUS0) Register (address = 01h) [reset = 01h]
Table 31.
STATUS0 Register Field Descriptions
10.6.3
Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
Table 32.
MODE0 Register Field Descriptions
10.6.4
Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
Table 33.
MODE1 Register Field Descriptions
10.6.5
Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
Table 34.
MODE2 Register Field Descriptions
10.6.6
Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
Table 35.
MODE3 Register Field Descriptions
10.6.7
Reference Configuration (REF) Register (address = 06h) [reset = 05h]
Table 36.
REF Register Field Descriptions
10.6.8
Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
Table 37.
OFCAL0, OFCAL1, OFCAL2 Registers Field Description
10.6.9
Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
Table 38.
FSCAL0, FSCAL1, FSCAL2 Registers Field Description
10.6.10
Current Source Multiplexer (I_MUX) Register (address = 0Dh) [reset = FFh]
Table 39.
I_MUX Register Field Descriptions
10.6.11
Current Source Magnitude (I_MAG) Register (address = 0Eh) [reset = 00h]
Table 40.
I_MAG Register Field Descriptions
10.6.12
Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
Table 41.
RESERVED Register Field Descriptions
10.6.13
MODE4 (MODE4) Register (address = 10h) [reset = 50h]
Table 42.
MODE4 Register Field Descriptions
10.6.14
PGA Alarm (STATUS1) Register (address = 11h) [reset = xxh]
Table 43.
STATUS1 Register Field Descriptions
10.6.15
Status 2 (STATUS2) Register (address = 12h) [reset = 0xh]
Table 44.
STATUS2 Register Field Descriptions
11
Application and Implementation
11.1
Application Information
11.1.1
Input Range
11.1.2
Input Overload
11.1.2.1
Input Signal Rate of Change (dV/dt)
11.1.3
Unused Inputs and Outputs
11.2
Typical Applications
11.2.1
±10-V Analog Input Module
11.2.1.1
Design Requirements
11.2.1.2
Detailed Design Procedure
11.2.1.3
Application Curves
11.2.2
Thermocouple Input With High Common-Mode Voltage
11.3
Initialization Setup
12
Power Supply Recommendations
12.1
Power-Supply Decoupling
12.2
Analog Power-Supply Clamp
12.3
Power-Supply Sequencing
12.4
5-V to ±15-V DC-DC Converter
13
Layout
13.1
Layout Guidelines
13.2
Layout Example
14
デバイスおよびドキュメントのサポート
14.1
ドキュメントのサポート
14.1.1
関連資料
14.2
ドキュメントの更新通知を受け取る方法
14.3
コミュニティ・リソース
14.4
商標
14.5
静電気放電に関する注意事項
14.6
Glossary
15
メカニカル、パッケージ、および注文情報
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RHB|32
MPQF130D
サーマルパッド・メカニカル・データ
RHB|32
QFND029X
発注情報
jajsgg2c_oa
jajsgg2c_pm
10.2
Functional Block Diagram