JAJSLQ5C April 2021 – September 2022 ADS127L11
PRODUCTION DATA
DRDY is the data-ready output signal. DRDY drives high when conversions are started or resynchronized, and drives low when conversion data are ready. DRDY is driven back high at the eighth SCLK during conversion data read. This behavior applies to the synchronized and the start/stop control modes. In one-shot control mode, DRDY stays low during conversion data read. If the ADC is programmed to enter standby mode (STBY_MODE bit = 1b), DRDY is driven back high three fCLK cycles after transitioning low. If conversion data are not read, DRDY pulses high just prior to the next falling edge. See the Section 8.4.6 section for details of DRDY operation for each of the conversion control modes. DRDY is an active output whether CS is high or low.