JAJSLQ5C April 2021 – September 2022 ADS127L11
PRODUCTION DATA
To operate the ADC with an external clock, apply the clock signal to the CLK pin, then program the CLK_SEL bit to 1b. A divide-by-eight option is available to operate the ADC in low-speed mode using the high-speed mode clock frequency (set the CLK_DIV bit = 1b). The clock can be decreased from nominal to yield specific data rates between the integer OSR values. However, the conversion noise when operating at the reduced clock frequency is the same as the higher clock frequency. Reducing the conversion noise is only possible by increasing the OSR value or changing the filter mode.
Clock jitter results in timing variations in the modulator sampling that leads to degraded SNR performance. A low-jitter clock is essential to meet data sheet SNR performance. For example, with a 200-kHz signal frequency, an external clock with < 10-ps (rms) jitter is required. For lower signal frequencies, the clock jitter requirement can be relaxed by –20 dB per decade of signal frequency. For example, with fIN = 20 kHz, a clock with 100-ps jitter can be used. Many types of RC oscillators exhibit high levels of jitter and should be avoided for ac signal measurement. Instead, use a crystal-based clock oscillator as the clock source. Avoid ringing on the clock input. A series resistor placed at the output of the clock buffer often helps reduce ringing.