JAJSLQ5C April 2021 – September 2022 ADS127L11
PRODUCTION DATA
The antialias filter consists of a passive first-order input filter, an active second-order filter, and a passive first-order output filter. The filter is fourth-order overall. The filter design accommodates the worst-case wideband filter OSR value (32), which results in less than two decades of frequency range between the Nyquist frequency at fDATA and the fMOD frequency. The fourth-order filter provides 90-dB rolloff over this frequency range. The filter rolloff at fMOD is the key function of the filter.
The THS4551 amplifier is selected for the active filter stage because of the 135-MHz gain-bandwidth product (GBP) and 50-ns settling time. The amplifier GBP is sufficient to maintain the filter rolloff at 12.8 MHz, even with the dc gain of 15 dB. For example, for applications where gain is desired, a 10-MHz amplifier has marginal GBP to fully support the required rolloff at the fMOD frequency. The settling time specification of the THS4551 also makes the device a good choice for driving the ADC sampled inputs.
The design of the active filter section begins with an equal-R assumption to reduce the number of component values to select. The dc gain of the filter is R3 / (R1 + R2). 1-kΩ resistors are selected to be low enough in value to keep resistor noise and amplifier input current noise from affecting the noise of the ADC.
The 1-kΩ input resistor is divided into two 499-Ω resistors (R1 and R2) to implement the first-order filter using C1. The first-order filter is decoupled from the second-order active filter, but shares R1 and R2 to determine each filter stage corner frequency. The corner frequency is given by C1 and the Thevenin resistance at the terminals of C1 (RTH = 2 × 250 Ω).
Given an arbitrary selection of R4 (2 × 499 Ω in this case), the values of the 2 × 180 pF (C3) feedback capacitors and the single 330-pF differential capacitor (C2) are calculated by the filter design equations given in the Design Methodology for MFB Filters in ADC Interface Applications application note. The design inputs are filter fO and filter Q for the multiple-feedback active filter topology. The differential capacitor (C4) is not part of the filter design but is used to improve filter phase margin. The 5-Ω resistors (R5) isolate the amplifier outputs from stray capacitance to further improve filter phase margin.
The final RC filter at the ADC inputs serves two purposes. First, the filter provides a fourth pole to the overall filter response, thereby increasing filter rolloff. The other purpose of the filter is a charge reservoir to filter the sampled input of the ADC. The charge reservoir reduces the instantaneous charge demand of the amplifier, maintaining low distortion and low gain error that otherwise can degrade because of incomplete amplifier settling. The input filter values are 2 × 22 Ω and 2.2 nF. The 22-Ω resistors are outside the THS4551 filter loop to isolate the amplifier outputs from the 2.2-nF capacitor to maintain phase margin.
Low voltage-coefficient C0G capacitors are used everywhere in the signal path for their low distortion properties. The amplifier gain resistors are 0.1% tolerance to provide best possible THD performance. The ADC VCM output connection to the amplifier VOCM input pin is optional because the same function is provided by the amplifier.
See the THS4551 data sheet for additional examples of active filter designs and application.