JAJSLQ5C April 2021 – September 2022 ADS127L11
PRODUCTION DATA
MIN | MAX | UNIT | ||
---|---|---|---|---|
CLK PIN | ||||
tc(CLK) | CLK period, high-speed mode | 38.2 | 2000 | ns |
CLK period, low-speed mode, CLK_DIV = 1b | 38.2 | 2000 | ||
CLK period, low-speed mode, CLK_DIV = 0b | 305 | 2000 | ||
tw(CLKL) | Pulse duration, CLK low | 17 | ns | |
Pulse duration, CLK low, low-speed mode | 128 | |||
tw(CLKH) | Pulse duration, CLK high | 17 | ns | |
Pulse duration, CLK high, low-speed mode | 128 | |||
SERIAL INTERFACE | ||||
tc(SC) | SCLK period | 20 | 1/(4 ∙ fDATA) | ns |
tw(SCL) | Pulse duration, SCLK low | 8 | ns | |
tw(SCH) | Pulse duration, SCLK high | 8 | ns | |
td(CSSC) | Delay time, first SCLK rising edge after CS falling edge | 10 | ns | |
tsu(DI) | Setup time, SDI valid before SCLK falling edge | 4 | ns | |
th(DI) | Hold time, SDI valid after SCLK falling edge | 6 | ns | |
td(SCCS) | Delay time, CS rising edge after final SCLK falling edge | 10 | ns | |
tw(CSH) | Pulse duration, CS high | 20 | ns | |
RESET PIN | ||||
tw(RSL) | Pulse duration, RESET low | 4 | t | |
td(RSSC) | Delay time, communication start after RESET rising edge or after SPI RESET pattern | 10000 | tCLK | |
START PIN | ||||
tw(STL) | Pulse duration, START low | 4 | tCLK | |
tw(STH) | Pulse duration, START high | 4 | tCLK | |
tsu(STCLK) | Setup time, START high before CLKIN rising edge (1) | 9 | ns | |
th(STCLK) | Hold time, START high after CLKIN rising edge (1) | 9 | ns | |
tsu(STDR) | Setup time, START falling edge or STOP bit before DRDY falling edge to stop next conversion (start/stop conversion mode) | 8 | tCLK |