SBAS446H December   2009  – February 2016 ADS1282-HT

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics
    5. 7.5  Electrical Characteristics (PW Package)
    6. 7.6  Timing Requirements
    7. 7.7  Pulse-Sync Timing Requirements
    8. 7.8  Reset Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Modulator Switching Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Noise Performance
      2. 8.3.2  Input-Referred Noise
      3. 8.3.3  Idle Tones
      4. 8.3.4  Operating Mode
      5. 8.3.5  Analog Inputs and Multiplexer
      6. 8.3.6  PGA (Programmable Gain Amplifier)
      7. 8.3.7  ADC
      8. 8.3.8  Modulator
      9. 8.3.9  Modulator Over-Range
      10. 8.3.10 Modulator Input Impedance
      11. 8.3.11 Modulator Over-Range Detection (MFLAG)
      12. 8.3.12 Voltage Reference Inputs (VREFP, VREFN)
      13. 8.3.13 Digital Filter
        1. 8.3.13.1 Sinc Filter Stage (Sinx/X)
        2. 8.3.13.2 FIR Stage
        3. 8.3.13.3 Group Delay and Step Response
          1. 8.3.13.3.1 Linear Phase Response
          2. 8.3.13.3.2 Minimum Phase Response
        4. 8.3.13.4 HPF Stage
      14. 8.3.14 Master Clock Input (CLK)
      15. 8.3.15 Synchronization (SYNC Pin and Sync Command)
      16. 8.3.16 Pulse-Sync Mode
      17. 8.3.17 Continuous-Sync Mode
      18. 8.3.18 Reset (RESET Pin and Reset Command)
      19. 8.3.19 Power-Down (PWDN Pin and Standby Command)
      20. 8.3.20 Power-On Sequence
      21. 8.3.21 Serial Interface
        1. 8.3.21.1 Serial Clock (SCLK)
        2. 8.3.21.2 Data Input (DIN)
        3. 8.3.21.3 Data Output (DOUT)
        4. 8.3.21.4 Data Ready (DRDY)
      22. 8.3.22 Data Format
      23. 8.3.23 Reading Data
        1. 8.3.23.1 Read Data Continuous
        2. 8.3.23.2 Read Data by Command
      24. 8.3.24 One-Shot Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modulator Output Mode
    5. 8.5 Programming
      1. 8.5.1 Commands
        1. 8.5.1.1  WAKEUP: Wake-Up from Standby Mode
        2. 8.5.1.2  STANDBY: Standby Mode
        3. 8.5.1.3  SYNC: Synchronize the A/D Conversion
        4. 8.5.1.4  RESET: Reset the Device
        5. 8.5.1.5  RDATAC: Read Data Continuous
        6. 8.5.1.6  SDATAC: Stop Read Data Continuous
        7. 8.5.1.7  RDATA: Read Data By Command
        8. 8.5.1.8  RREG: Read Register Data
        9. 8.5.1.9  WREG: Write to Register
        10. 8.5.1.10 OFSCAL: Offset Calibration
        11. 8.5.1.11 GANCAL: Gain Calibration
      2. 8.5.2 Calibration Commands
        1. 8.5.2.1 OFSCAL Command
        2. 8.5.2.2 GANCAL Command
      3. 8.5.3 User Calibration
      4. 8.5.4 Configuration Guide
    6. 8.6 Register Maps
      1. 8.6.1 ADS1282-HT Register Map Information
      2. 8.6.2 ID Register
      3. 8.6.3 Configuration Registers
        1. 8.6.3.1 Configuration Register 0
        2. 8.6.3.2 Configuration Register 1
      4. 8.6.4 HPF1 and HPF0
        1. 8.6.4.1 High-Pass Filter Corner Frequency, Low Byte
        2. 8.6.4.2 High-Pass Filter Corner Frequency, High Byte
      5. 8.6.5 OFC2, OFC1, OFC0
        1. 8.6.5.1 Offset Calibration, Low Byte
        2. 8.6.5.2 Offset Calibration, Mid Byte
        3. 8.6.5.3 Offset Calibration, High Byte
      6. 8.6.6 FSC2, FSC1, FSC0
        1. 8.6.6.1 Full-Scale Calibration, Low Byte
        2. 8.6.6.2 Full-Scale Calibration, Mid Byte
        3. 8.6.6.3 Full-Scale Calibration, High Byte
      7. 8.6.7 Offset and Full-Scale Calibration Registers
        1. 8.6.7.1 OFC[2:0] Registers
        2. 8.6.7.2 FSC[2:0] Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Geophone Interface Typical Application
        1. 9.2.1.1 Detailed Design Procedure
      2. 9.2.2 Digital Connection to a Field Programmable Gate Array (FPGA) Device Typical Application
        1. 9.2.2.1 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 HPF Transfer Function
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11 Device and Documentation Support

11.1 Device Support

Table 19. FIR Stage Coefficients

COEFFICIENT SECTION 1 SECTION 2 SECTION 3 SECTION 4
SCALING = 1 / 8388608 SCALING = 134217728 SCALING = 134217728
LINEAR PHASE MINIMUM PHASE LINEAR PHASE MINIMUM PHASE
b0 –10944 –774 –73 819 –132 11767
b1 0 0 –874 8211 –432 133882
b2 103807 8994 –4648 44880 –75 769961
b3 0 0 –16147 174712 2481 2940447
b4 –507903 –51663 –41280 536821 6692 8262605
b5 0 0 –80934 1372637 7419 17902757
b6 2512192 199523 –120064 3012996 –266 30428735
b7 4194304 0 –118690 5788605 –10663 40215494
b8 2512192 –629120 –18203 9852286 –8280 39260213
b9 0 0 224751 14957445 10620 23325925
b10 –507903 2570188 580196 20301435 22008 –1757787
b11 0 4194304 893263 24569234 348 –21028126
b12 103807 2570188 891396 26260385 –34123 –21293602
b13 0 0 293598 24247577 –25549 –3886901
b14 –10944 –629120 –987253 18356231 33460 14396783
b15 0 –2635779 9668991 61387 16314388
b16 199523 –3860322 327749 –7546 1518875
b17 0 –3572512 –7171917 –94192 –12979500
b18 –51663 –822573 –10926627 –50629 –11506007
b19 0 4669054 –10379094 101135 2769794
b20 8994 12153698 –6505618 134826 12195551
b21 0 19911100 –1333678 –56626 6103823
b22 –774 25779390 2972773 –220104 –6709466
b23 27966862 5006366 –56082 –9882714
b24 Only half shown; symmetric starting with b22. 4566808 263758 –353347
b25 2505652 231231 8629331
b26 126331 –215231 5597927
b27 –1496514 –430178 –4389168
b28 –1933830 34715 –7594158
b29 –1410695 580424 –428064
b30 –502731 283878 6566217
b31 245330 –588382 4024593
b32 565174 –693209 –3679749
b33 492084 366118 –5572954
b34 231656 1084786 332589
b35 –9196 132893 5136333
b36 –125456 –1300087 2351253
b37 –122207 –878642 –3357202
b38 –61813 1162189 –3767666
b39 –4445 1741565 1087392
b40 22484 –522533 3847821
b41 22245 –2490395 919792
b42 10775 –688945 –2918303
b43 940 2811738 –2193542
b44 –2953 2425494 1493873
b45 –2599 –2338095 2595051
b46 –1052 –4511116 –79991
b47 –43 641555 –2260106
b48 214 6661730 –963855
b49 132 2950811 1482337
b50 33 –8538057 1480417
b51 –10537298 –586408
b52 9818477 –1497356
b53 41426374 –168417
b54 56835776 1166800
b55 Only half shown; symmetric starting with b53. 644405
b56 –675082
b57 –806095
b58 211391
b59 740896
b60 141976
b61 –527673
b62 –327618
b63 278227
b64 363809
b65 –70646
b66 –304819
b67 –63159
b68 205798
b69 124363
b70 –107173
b71 –131357
b72 31104
b73 107182
b74 15644
b75 –71728
b76 –36319
b77 38331
b78 38783
b79 –13557
b80 –31453
b81 –1230
b82 20983
b83 7729
b84 –11463
b85 –8791
b86 4659
b87 7126
b88 –732
b89 –4687
b90 –976
b91 2551
b92 1339
b93 –1103
b94 –1085
b95 314
b96 681
b97 16
b98 –349
b99 –96
b100 144
b101 78
b102 –46
b103 –42
b104 9
b105 16
b106 0
b107 –4
Equation 15. ADS1282-HT q_hpf_gerr_bas418.gif

See HPF Stage for an example of how to use this equation.

11.1.1 HPF Transfer Function

Equation 16. ADS1282-HT q_hpf2_bas418.gif

where b is calculated as shown in Equation 17:

Equation 17. ADS1282-HT q_b_bas378.gif

Table 20. tDR Time for Data Ready (Sinc Filter)

ƒDATA ƒCLK(1)
128k 440
64k 616
32k 968
16k 1672
8k 2824
(1) For SYNC and Wake-Up commands, ƒCLK = number of CLK cycles from next rising CLK edge directly after eighth rising SCLK edge to DRDY falling edge. For Wake-Up command only, subtract two ƒCLK cycles.

Table 20 is referenced by Pulse-Sync Timing Requirements.

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

    TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
    Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.