JAJSGE8B March   2016  – October 2018 ADS1282-SP

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements
    7. 7.7  Pulse-Sync Timing Requirements
    8. 7.8  Reset Timing Requirements
    9. 7.9  Read Data Timing Requirements
    10. 7.10 Switching Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Noise Performance
      2. 8.3.2  Input-Referred Noise
      3. 8.3.3  Idle Tones
      4. 8.3.4  Operating Mode
      5. 8.3.5  Analog Inputs and Multiplexer
      6. 8.3.6  PGA (Programmable Gain Amplifier)
      7. 8.3.7  ADC
      8. 8.3.8  Modulator
      9. 8.3.9  Modulator Over-Range
      10. 8.3.10 Modulator Input Impedance
      11. 8.3.11 Modulator Over-Range Detection (MFLAG)
      12. 8.3.12 Voltage Reference Inputs (VREFP, VREFN)
      13. 8.3.13 Digital Filter
        1. 8.3.13.1 Sinc Filter Stage (Sinx/X)
        2. 8.3.13.2 FIR Stage
        3. 8.3.13.3 Group Delay and Step Response
          1. 8.3.13.3.1 Linear Phase Response
          2. 8.3.13.3.2 Minimum Phase Response
        4. 8.3.13.4 HPF Stage
      14. 8.3.14 Master Clock Input (CLK)
      15. 8.3.15 Synchronization (SYNC Pin and Sync Command)
      16. 8.3.16 Pulse-Sync Mode
      17. 8.3.17 Continuous-Sync Mode
      18. 8.3.18 Reset (RESET Pin and Reset Command)
      19. 8.3.19 Power-Down (PWDN Pin and Standby Command)
      20. 8.3.20 Power-On Sequence
      21. 8.3.21 Serial Interface
        1. 8.3.21.1 Serial Clock (SCLK)
        2. 8.3.21.2 Data Input (DIN)
        3. 8.3.21.3 Data Output (DOUT)
        4. 8.3.21.4 Data Ready (DRDY)
      22. 8.3.22 Data Format
      23. 8.3.23 Reading Data
        1. 8.3.23.1 Read Data Continuous
        2. 8.3.23.2 Read Data by Command
      24. 8.3.24 One-Shot Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modulator Output Mode
    5. 8.5 Programming
      1. 8.5.1 Commands
        1. 8.5.1.1  WAKEUP: Wake-Up from Standby Mode
        2. 8.5.1.2  STANDBY: Standby Mode
        3. 8.5.1.3  SYNC: Synchronize the A/D Conversion
        4. 8.5.1.4  RESET: Reset the Device
        5. 8.5.1.5  RDATAC: Read Data Continuous
        6. 8.5.1.6  SDATAC: Stop Read Data Continuous
        7. 8.5.1.7  RDATA: Read Data By Command
        8. 8.5.1.8  RREG: Read Register Data
        9. 8.5.1.9  WREG: Write to Register
        10. 8.5.1.10 OFSCAL: Offset Calibration
        11. 8.5.1.11 GANCAL: Gain Calibration
      2. 8.5.2 Calibration Commands
        1. 8.5.2.1 OFSCAL Command
        2. 8.5.2.2 GANCAL Command
      3. 8.5.3 User Calibration
      4. 8.5.4 Configuration Guide
    6. 8.6 Register Maps
      1. 8.6.1 ADS1282-SP Register Map Information
      2. 8.6.2 ID Register
        1. Table 13. ID Register Field Descriptions
      3. 8.6.3 Configuration Registers
        1. 8.6.3.1 Configuration Register 0
          1. Table 14. Configuration Register 0 Field Descriptions
        2. 8.6.3.2 Configuration Register 1
          1. Table 15. Configuration Register 1 Field Descriptions
      4. 8.6.4 HPF1 and HPF0
        1. 8.6.4.1 High-Pass Filter Corner Frequency, Low Byte
        2. 8.6.4.2 High-Pass Filter Corner Frequency, High Byte
      5. 8.6.5 OFC2, OFC1, OFC0
        1. 8.6.5.1 Offset Calibration, Low Byte
        2. 8.6.5.2 Offset Calibration, Mid Byte
        3. 8.6.5.3 Offset Calibration, High Byte
      6. 8.6.6 FSC2, FSC1, FSC0
        1. 8.6.6.1 Full-Scale Calibration, Low Byte
        2. 8.6.6.2 Full-Scale Calibration, Mid Byte
        3. 8.6.6.3 Full-Scale Calibration, High Byte
      7. 8.6.7 Offset and Full-Scale Calibration Registers
        1. 8.6.7.1 OFC[2:0] Registers
        2. 8.6.7.2 FSC[2:0] Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Thermocouple Temperature Sensing Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Digital Connection to a Field Programmable Gate Array (FPGA) Device Typical Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 HPF伝達関数
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

AVDD = 2.5 V, AVSS = –2.5 V, ƒCLK(1) = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1, and ƒDATA = 1000 SPS, over operating temperature range, unless otherwise noted. Typical values are TJ = 25°C. A total ionizing dose of 50 kRad (Si) exposure at a low dose rate of < 10 mRads (Si)/s, post tested at 25°C.
PARAMETER TEST CONDITIONS 5962L1423101VXC 5962L1423102VXC UNIT
MIN TYP MAX MIN TYP MAX
ANALOG INPUTS
Full-scale input voltage VIN = (AINP – AINN) (VREFP – VREFN) / (PGA) (VREFP – VREFN) / (PGA) Vpp-diff
AINP or
AINN		 Absolute input range AVSS + 0.7 AVDD – 1.25 AVSS + 0.7 AVDD – 1.25 V
PGA input voltage noise density 5 5 nV/√Hz
Differential input impedance(2) 1 1 GΩ
Common-mode input impedance 100 100 MΩ
Input bias current 1 1 nA
Crosstalk ƒ = 31.25 Hz –128 –128 dB
MUX on-resistance 30 30 Ω
PGA OUTPUT (CAPP, CAPN)
Absolute output range AVSS + 0.4 AVDD – 0.4 AVSS + 0.4 AVDD – 0.4 V
PGA differential output impedance 600 600 Ω
Output impedance tolerance ±10% ±10%
External bypass capacitance 10 100 10 100 nF
Modulator differential input impedance 55 55 kΩ
AC PERFORMANCE
SNR Signal-to-noise ratio(3) 112 124 112 124 dB
THD Total harmonic distortion(4) PGA = 1...16 –122 –99 –122 –101 dB
PGA = 32 –117 –90 –117 –92
PGA = 64 –115 –115
SFDR Spurious-free dynamic range 123 123 dB
DC PERFORMANCE
Resolution No missing codes 31 31 bits
ƒDATA Data rate FIR filter mode 250 4000 250 4000 SPS
SINC filter mode 8000 128000 8000 128000
Integral nonlinearity (INL)(5) Differential input 0.00005 0.0090 0.00005 0.0090 % FSR(6)
Offset error 0.0170 0.0170
Offset error after calibration(7) Shorted input 50 200 50 200 μV
Offset drift 750 750
Gain error(8) 1 1 μV
Gain error after calibration(7) 0.02 0.02 μV/°C
Gain drift –1.5% –1.0% –0.5% –1.5% –1.0% –0.5%
Gain matching(12) 0.0002% 0.0002%
Common-mode rejection PGA = 1 2 2 ppm/°C
PGA = 16 9 9
0.3% 0.8% 0.3% 0.8%
ƒCM = 60 Hz(9) 82 110 82 110 dB
AVDD,
AVSS		 Power-supply rejection ƒPS = 60 Hz(9) 80 90 80 90 dB
Post 50 kRads (Si), TJ = 25°C(14) 64 90 64 90 dB
DVDD 90 115 90 115 dB
VOLTAGE REFERENCE INPUTS
Reference input voltage (VREF = VREFP – VREFN) 0.5 5 (AVDD – AVSS) + 0.2 0.5 5 (AVDD – AVSS) + 0.2 V
VREFN Negative reference input AVSS – 0.1 VREFP – 0.5 AVSS – 0.1 VREFP – 0.5 V
VREFP Positive reference input VREFN + 0.5 AVDD + 0.1 VREFN + 0.5 AVDD + 0.1 V
Reference input impedance 85 85 kΩ
DIGITAL FILTER RESPONSE
Passband ripple ±0.003 ±0.003 dB
Passband (–0.01 dB) 0.375 × ƒDATA 0.375 × ƒDATA Hz
Bandwidth (–3 dB) 0.413 × ƒDATA 0.413 × ƒDATA Hz
High-pass filter corner 0.1 10 0.1 10 Hz
Stop band attenuation(10) 135 135 dB
Stop band 0.500 × ƒDATA 0.500 × ƒDATA Hz
Group delay Minimum phase filter(13) 5 / ƒDATA 5 / ƒDATA s
Settling time (latency) 31 / ƒDATA 31 / ƒDATA s
Minimum phase filter 62 / ƒDATA 62 / ƒDATA s
Linear phase filter 62 / ƒDATA 62 / ƒDATA s
DIGITAL INPUT/OUTPUT
VIH 0.8 × DVDD DVDD 0.8 × DVDD DVDD V
VIL DGND 0.2 × DVDD DGND 0.2 × DVDD V
VOH IOH = 1 mA 0.8 × DVDD 0.8 × DVDD V
VOL IOL = 1 mA 0.2 × DVDD 0.2 × DVDD V
Input leakage 0 < VDIGITAL IN < DVDD ±10 ±10 μA
ƒCLK Clock input 1 4.096 1 4.096 MHz
ƒSCLK Serial clock rate ƒCLK / 2 ƒCLK / 2 MHz
POWER SUPPLY
AVSS –2.6 0 –2.6 0 V
AVDD AVSS + 4.75 AVSS + 5.25 AVSS + 4.75 AVSS + 5.25 V
DVDD 1.75 3.6 1.75 3.6 V
AVDD, AVSS current High-resolution mode 4.5 7.2 4.5 6.5 |mA|
Post 50 kRads (Si), TJ = 25°C(14) 11 11 |mA|
Power-down mode –200 200 -200 200 |μA|
Post 50 kRads (Si), TJ = 25°C(14) 5 5 |mA|
Standby mode –200 200 -200 200 |μA|
Post 50 kRads (Si), TJ = 25°C(14) 5 5 |mA|
DVDD current High-resolution mode 0.6 1.5 0.6 1.2 mA
Power-down mode(11) 32 120 32 120 μA
Standby mode 73 175 73 175 μA
Power dissipation High-resolution mode 25 41 25 41 mW
Post 50 kRads (Si), TJ = 25°C(14) 60 60 mW
Power-down mode 0.45 0.95 0.45 0.95 mW
Post 50 kRads (Si), TJ = 25°C(14) 25.4 25.4 mW
Standby mode 0.58 1.1 0.58 1.1 mW
Post 50 kRads (Si), TJ = 25°C(14) 25.4 25.4 mW
(1) ƒCLK = system clock.
(2) Input impedance is improved by disabling input chopping (CHOP bit = 0).
(3) VIN = 20 mVDC / PGA, see Table 1.
(4) VIN = 31.25 Hz, –0.5 dBFS.
(5) Best-fit method.
(6) FSR: Full-scale range = ±VREF / (2 × PGA).
(7) Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings).
(8) The PGA output impedance and the modulator input impedance results in –1% systematic gain error.
(9) ƒCM is the input common-mode frequency. ƒPS is the power-supply frequency.
(10) Input frequencies in the range of NƒCLK / 512 ± ƒDATA / 2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency ranges intermodulation = 120 dB, typ.
(11) CLK input stopped.
(12) Gain match relative to PGA = 1.
(13) At DC. See Figure 42.
(14) The maximum limit applies to SMD 5962L14231 post 50 kRads (Si) test at 25°C.